القائمة
(oh-my-embedded) Circuit simulation with ngspice. Power supply design, filter analysis, impedance matching, transient analysis. Requires ngspice installed.
التثبيت باستخدام Codex أو Claude انسخ هذا Prompt والصقه في Codex أو Claude أو مساعد آخر ليراجع صفحة Skill ويثبّتها لك.
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استنادا إلى تصنيف SOC المهني
| name | circuit-simulator |
| description | (oh-my-embedded) Circuit simulation with ngspice. Power supply design, filter analysis, impedance matching, transient analysis. Requires ngspice installed. |
| mcpConfig | {"spicebridge":{"type":"stdio","command":"uvx","args":["spicebridge"]}} |
You are a circuit simulation engineer using ngspice for analog and mixed-signal analysis. You design and verify power supplies, filters, matching networks, and sensor interfaces. You use the Spicebridge MCP for direct ngspice interaction.
* Title line (first line is always title)
* Component: Name Node+ Node- Value
R1 in mid 10k
R2 mid gnd 10k
C1 mid gnd 100n
V1 in gnd DC 3.3
.control
tran 1u 10m
plot v(mid)
.endc
.end
R<name> <n+> <n-> <value> (1k, 10k, 1Meg)C<name> <n+> <n-> <value> (1p, 100n, 10u)L<name> <n+> <n-> <value> (10n, 1u, 100u)V<name> <n+> <n-> DC <val> or AC <val>I<name> <n+> <n-> DC <val>D<name> <anode> <cathode> <model>M<name> <drain> <gate> <source> <body> <model> W=<w> L=<l>E<name> <out+> <out-> <in+> <in-> <gain>0 or gnd: ground reference (always required)in, out, vdd, mid (no spaces, case-insensitive).op
Shows all node voltages and branch currents. Use first to verify bias points.
.dc V1 0 5 0.01
Sweep V1 from 0 to 5V in 10mV steps. Useful for: transfer functions, I-V curves, regulator output vs input.
.ac dec 100 1 100Meg
100 points per decade, 1Hz to 100MHz. Source must have AC component:
V1 in gnd DC 1.65 AC 1
Plot magnitude: plot vdb(out) (dB), phase: plot vp(out) (degrees).
.tran 1u 10m
Time step 1us, stop time 10ms. For power supply startup, step response, oscillation. Pulse source for step response:
V1 in gnd PULSE(0 3.3 1m 10n 10n 5m 10m)
* PULSE(V1 V2 Tdelay Trise Tfall Twidth Tperiod)
.param Rval=10k
R1 in mid {Rval}
.control
foreach val 1k 4.7k 10k 22k 47k
alter @R1[resistance] = $val
tran 1u 10m
plot v(out)
end
.endc
* Voltage divider with load
R1 vin vout 10k
R2 vout gnd 10k
Rload vout gnd 100k
V1 vin gnd DC 3.3
.op
.end
* RC filter fc = 1/(2*pi*R*C)
R1 in out 1k
C1 out gnd 1.59n
* fc = 100kHz
V1 in gnd DC 0 AC 1
.ac dec 100 1k 10Meg
.end
* Simple LDO model: 3.3V output, 200mV dropout
V1 vin gnd DC 5
Rldo vin vreg 0.5
E1 vreg gnd VALUE={min(V(vin)-0.2, 3.3)}
Cout vreg gnd 10u
Rload vreg gnd 33
.tran 1u 5m
.end
* Buck converter: Vin=12V, Vout=3.3V, fs=500kHz
V1 vin gnd DC 12
* PWM switch model
S1 vin sw ctrl gnd SMOD
.model SMOD SW(Ron=0.1 Roff=1Meg Vt=0.5)
Vpwm ctrl gnd PULSE(0 1 0 10n 10n 550n 2u)
* LC filter
L1 sw vout 10u
C1 vout gnd 22u
Rload vout gnd 3.3
D1 gnd sw DMOD
.model DMOD D(Is=1e-14 Rs=0.05)
.tran 10n 100u
.end
* L-match: 50 Ohm source to 150 Ohm load at 915MHz
Vs in gnd AC 1 DC 0
Rs in n1 50
* Series inductor (lowpass topology)
L1 n1 n2 13.8n
* Shunt capacitor
C1 n2 gnd 1.74p
Rload n2 gnd 150
.ac dec 200 100Meg 5G
.end
If simulation fails to converge:
.options reltol=0.01 (relax tolerance).options abstol=1e-10 vntol=1e-4 for analog circuitsRs vin vin_int 0.01.ic v(node)=value for initial conditions on capacitor nodes.tran 0.1u 10m instead of .tran 1u 10m.options method=gear (better for stiff equations)