chuanseng-ng

Distil append-only experiences.jsonl run records into per-domain knowledge.md summaries for the analog design agents. Use after enough runs accumulate to merge new convergence fixes, sizing recipes, PDK quirks, and tool flags into the Tier-2 knowledge file.

Analog circuit (schematic) design — topology selection, device sizing via gm/Id, biasing, schematic capture, pre-layout ERC, and design review. Use when designing an op-amp, comparator, bandgap, LDO, bias generator, or any analog block from a block specification through to a sign-off-ready schematic and netlist.

EDA tool detection, wrapper deployment, and MCP configuration for analog/mixed-signal + RF design environments. Use when setting up a workstation, verifying tool availability before a domain flow, or generating per-tool install scripts with TCL modulefiles.

Floorplan, generate matched devices, and place/route analog blocks with symmetry, shielding, and matching constraints to a clean, DRC-ready layout. Use when turning a sign-off-ready schematic into a GDS layout, or servicing a fix_request that repairs the layout after a DRC/LVS or parasitic-degradation failure.

Run DRC, LVS, antenna/ERC, and density/DFM checks on an analog layout and sign off a physically-clean GDS. Use when verifying a custom layout against the foundry rule deck and the source netlist, or re-validating after a custom-layout fix_request was serviced. Opens fix_requests routed to custom-layout on DRC/LVS failures.

Cross-domain loop orchestration for the analog/mixed-signal + RF design pipeline. Provides the fix_request protocol, iteration-cap logic, the authoritative design_state.json constraints schema, failure classification, and approval checkpoints. Use when driving the closed-loop spec↔circuit↔layout feedback cycle.

Solve the electromagnetics of an on-chip passive or antenna (inductor, transformer, transmission line, balun, antenna), extract a converged passive S-parameter model, and fit a lumped equivalent for circuit-level RF simulation. Use when building the passive model rf-design consumes, or to service an rf-design fix_request (route_to: em-modeling) by re-solving the passive. Loop-backs are stage-local (passivity/fit → meshing/geometry_definition); passivity is a hard gate; a fundamental geometry/stackup gap escalates.

Design and verify an RF/mmWave block (LNA, mixer, VCO, PLL, PA): topology selection and matching, S-parameter, harmonic-balance, Pnoise/PAC, IP3, and load-pull analyses, signed off against the RF spec table across corners. Use when designing or re-running an RF block. Loop-backs are stage-local first (spec/stability → topology_matching, convergence → harmonic_balance); when a cap is exhausted RF opens a cross-domain fix_request (circuit-design for device rework, em-modeling for a passive shortfall) and reads the EM-modeling passive model as a data dependency.

Distil accumulated experience records (experiences.jsonl) into updated domain knowledge summaries (knowledge.md) for any chip-design domain. Run after every 10 orchestrator sessions, or on demand when a domain has collected new issue/fix patterns.

Cross-domain loop orchestration for the chip design pipeline. Provides the fix_request protocol, iteration-cap logic, escalation templates, and dispatch patterns for routing verification/formal failures to the RTL orchestrator and back. Use when driving the closed-loop verification↔RTL feedback cycle.

High-Level Synthesis — C/C++ algorithm analysis, HLS directive optimisation, synthesis execution, and co-simulation verification. Use when converting C/C++ to synthesisable RTL, optimising for latency/throughput/area targets using pragmas, or verifying that generated RTL matches the golden C model.

Static timing analysis — multi-corner constraint validation, setup and hold analysis, timing exception review, and ECO guidance for closure. Use when running timing analysis on a design, reviewing timing violations, guiding ECO fixes, or performing timing sign-off for tape-out.

Microarchitecture exploration, PPA estimation, risk assessment, and architecture sign-off for digital chip design. Use when evaluating design candidates, estimating power/area/performance, assessing technical risk, or producing a microarchitecture document for handoff to RTL design.

Design for Test — scan architecture planning, scan insertion, ATPG pattern generation, MBIST for embedded memories, and JTAG boundary scan. Use when planning a DFT strategy, inserting scan, generating test patterns, or verifying that a chip will be testable in manufacturing.

Formal property verification (FPV) and logical equivalence checking (LEC). Use when proving design properties exhaustively, checking RTL vs gate-level netlist equivalence, verifying CDC crossings formally, or closing verification coverage gaps that simulation cannot efficiently reach.

FPGA prototyping — ASIC-to-FPGA RTL adaptation, multi-FPGA partitioning, synthesis and timing closure on FPGA, hardware bring-up, and software validation on the prototype. Use when porting an ASIC design to Xilinx or Intel FPGA for pre-silicon software development and hardware validation.