hardware-design

Use when working on synthesizable RTL, custom AXI-Lite IP, protocol cores, register maps, hardware-facing Verilog/SystemVerilog changes, or simulation testbenches in this PYNQ-Z1 hardware design repository.

Use when working on PYNQ Python overlays, MMIO drivers, board-side runtime clients, notebooks, TCP socket transmission, PC-side receive services, payload protocols, storage, or analysis handoff in this sleep monitoring repository.

Use when working on Vivado projects, custom IP packaging, IP repositories, Block Design integration, Zynq PS wiring, AXI interconnects, XDC constraints, bitstream generation, or PYNQ overlay export in this PYNQ-Z1 repository.