tv80

Synthesize TV80 RTL using Yosys. Use when: running synthesis, checking area/cell counts, generating netlists, analyzing logic, checking for synthesis warnings or errors, reporting gate-level statistics.

Build TV80 Chisel RTL by running sbt. Use when: building Chisel code, generating Verilog from Chisel, running sbt runMain, compiling tv80 Chisel sources, checking for Chisel build errors.

Run TV80 verification tests using Cocotb and Verilator. Use when: running simulations, executing testbench, building test programs, checking test results, running a specific test case, collecting coverage.