demo

Generate repository-ready ring bus topology Python and test driver files from a markdown architecture description, then optionally run the generated test script to produce build_logic RTL output and execute rtl_qc VCS compilation. Use when the user provides a .md ring bus architecture, wants MemTopo.py plus test_xxx.py, asks for markdown to rtl generation, ring_for_pd style topology generation, or wants an end-to-end markdown to build_logic to VCS flow.

Use when processing RTL modules at the microarchitecture level - including FIFO, state machines, counters, arbiters, decoders, or any Verilog/SystemVerilog hardware design. Load this skill immediately upon identifying RTL design tasks, before diving into brainstorming，planning or implementation.

verification_workflow 流水线的第 8 步。读取第 4 步输出的 verification-sim-tc-defines.md 中每条 TC 的 Checker 字段，编写两类检查代码：（1）在接口文件中实现 SVA assert property 捕获时序不变式；（2）若 tb-arch 规划了 Scoreboard，实现 Scoreboard 的数据比对逻辑。若存在 UVM/TB coding style 相关 skill，在开始编码前必须先加载。输出为接口文件中的 SVA 属性块 + tb/env/<dut>_scoreboard.sv。触发条件：由 verification_workflow 在第 8 步调用，或用户直接需要为已定义的 TC Checker 生成断言或 Scoreboard 代码时触发。

verification_workflow 流水线的第 7 步。读取第 4 步输出的 verification-sim-tc-defines.md 中每条 TC 的 Coverage 字段，结合第 5 步输出的 verification-tb-arch.md 中的 Monitor/Subscriber 分配，为每条 TC 编写 UVM 功能覆盖率代码（covergroup / coverpoint / bins）。若存在 UVM/TB coding style 相关 skill，在开始编码前必须先加载。输出为 tb/env/<dut>_func_cov.sv 覆盖率收集器文件。触发条件：由 verification_workflow 在第 7 步调用，或用户直接需要为已定义的 TC Coverage 生成功能覆盖率代码时触发。

verification_workflow 流水线的第 6 步。读取第 4 步输出的 verification-sim-tc-defines.md 中每条 TC 的 Stim 字段，结合第 5 步输出的 verification-tb-arch.md 中的 Agent/Sequencer 分配，为每条 TC 编写 UVM Sequence 激励代码。若存在 UVM/TB coding style 相关 skill，在开始编码前必须先加载。输出为 tb/sequences/ 目录下每条 TC 对应的 .sv 激励序列文件。触发条件：由 verification_workflow 在第 6 步调用，或用户直接需要为已定义的 TC Stim 生成 UVM Sequence 代码时触发。

verification_workflow 流水线的第 5 步。读取第 4 步输出的 verification-sim-tc-defines.md，分析所有测试用例三元组的 Stim/Coverage/Checker 需求，决策如何构建基于 UVM 的 Testbench 架构——包括需要哪些组件、组件间的连接关系、哪些组件可复用已有 VIP、哪些组件需要自行开发。输出为 verification-tb-arch.md，包含完整的 TB 组件清单、层次结构图、接口/VIP 决策以及开发任务分配。触发条件：由 verification_workflow 在第 5 步调用，或用户直接需要为一批 SIM 测试用例规划 UVM TB 架构时触发。

verification_workflow 流水线的第 9 步。读取第 5 步输出的 verification-tb-arch.md，实现 UVM Testbench 的结构性骨架（接口 + clocking block、seq_item、Driver、Monitor、Agent、Package、Ref Model、Virtual Sequencer、Env 连接层、Tests、tb_top），并整合第 6~8 步已生成的 sequences / fcov / checker 代码，输出完整 tb_filelist.f。若存在 UVM/TB coding style 相关 skill，在开始编码前必须先加载。触发条件：由 verification_workflow 在第 9 步调用，或用户直接需要为已设计的 TB 架构生成结构性骨架代码时触发。

verification_workflow 流水线的第 4 步。读取第 3 步输出的 verification-strategy.md，筛选所有手段为 SIM 的测试点，并为每个测试点精确定义三元组：Stim（如何触发）、Coverage（系统必须出现的状态）、Checker（系统绝不能出现的状态）。输出为 verification-sim-tc-defines.md，可直接指导 testbench 激励、覆盖组和断言的实现。触发条件：由 verification_workflow 在第 4 步调用，或用户直接需要为 SIM 测试点定义具体用例三元组时触发。

"verification_workflow 流水线的第 3 步。根据第 2 步生成的测试点列表，为每条测试点确定最优的验证手段——回答每条测试点"应使用何种手段验证"。可用手段只有两种：动态仿真（SIM）或形式化验证（FORMAL）。输出为测试点到验证手段的映射策略表，并附带决策依据。触发条件：由 verification_workflow 在第 3 步调用，或用户直接需要为一组测试点规划验证策略时触发。"

verification_workflow 流水线的第 1 步。通过与用户交互，分析 DUT Spec 和 RTL 代码，定义验证目标。输出涵盖功能验证、性能验证、连通性验证的结构化验证目标文档。触发条件：由 verification_workflow 在第 1 步调用，或用户直接需要为某个 IP/模块定义验证范围/目标时触发。

"verification_workflow 流水线的第 2 步。将验证目标（来自第 1 步）分解为完整的、按类别划分的测试点列表——回答"需要验证什么"，而不关心"怎么验证"。测试点来源包括：Spec 显式要求、隐式推断、行业/协议规范、历史教训。触发条件：由 verification_workflow 在第 2 步调用，或用户直接需要为某个 IP/模块分解测试点时触发。"

重要：用于任何芯片 IP/模块验证规划任务时必须加载。定义强制性的九步串行工作流（verification-target → verification-testpoint → verification-strategy → verification_sim_tc_define → verification_sim_tb_arch → verification_sim_stim_writer → verification_sim_fcov_writer → verification_sim_checker_writer → verification_sim_tb_writer），并按顺序编排各子 skill 的加载。若不加载本 skill，将跳过关键阶段，产生不完整的临时验证计划。触发条件：任何涉及为 Verilog/SystemVerilog IP、模块或 RTL 块进行规划/定义/准备/验证/策略制定的任务——尤其是从头开始时。

Guide for RTL/IP design — new designs from scratch, existing-RTL documentation, or existing-doc implementation. Covers spec-first workflow, user confirmation gates, project structure, RTL/filelist/testbench/testcase/SDC synchronization. Use when user asks to design new IP, write docs for existing RTL, implement RTL from existing docs, add testbenches, or any combination of RTL design deliverables.

Read and analyze chip verification coverage databases (UCIS XML, Synopsys VDB, Cadence UCD, Siemens UCDB) using the cov_reader CLI tool and Python API. Use this skill whenever the user mentions coverage data, coverage reports, coverage holes, uncovered bins, covergroups, line/toggle/branch/condition/FSM/assertion coverage, or wants to inspect verification results. Also trigger when the user mentions waivers, exclusions, .cwv.yaml files, .el files, .vRefine files, coverage filtering, excluding DFT signals, or wants to see "effective coverage" after excluding known gaps. Also trigger when you see .xml (UCIS), .vdb, .ucd, .ucdb file extensions in the workspace, when the user mentions coverage metrics like "line coverage 80%", "toggle coverage", "coverpoint", "cross coverage", or when debugging verification gaps — even if they don't explicitly say "cov_reader".

Use when processing RTL modules at the microarchitecture level - including FIFO, state machines, counters, arbiters, decoders, or any Verilog/SystemVerilog hardware design. Load this skill immediately upon identifying RTL design tasks, before diving into brainstorming，planning or implementation.

CRITICAL: Load for ANY RTL/chip IP design task. Defines the mandatory step-by-step workflow (architecture → spec → RTL → verification → PPA) you MUST follow when creating, modifying, or verifying an IP or module. Without this skill you will skip phases and produce incomplete designs. Triggers: any task involving design/create/implement/build/modify/verify a Verilog/SystemVerilog IP, module, or RTL block.

Use when analyzing, auditing, or modifying cross-references between skills. Triggers: skill not loading despite matching description, need to understand skill dependency topology, adding a new link from one skill to another, diagnosing why a target skill has low load rate, or reviewing which skills should reference a given target. Pairs with `dev-skill-load-test` for AB test verification.

Use when testing skill loading effectiveness, verifying subagent compliance with skill requirements, or conducting batch skill validation tests. Triggers when you need to validate that skills load correctly across multiple test cases.

Fast RTL PPA analysis using Yosys + OpenSTA. Use this skill whenever the user mentions quick synthesis, gate count estimation, logic depth analysis, flip-flop count, combinational cell count, design hierarchy exploration after synthesis, or fast PPA (Power/Performance/Area) estimation. Also trigger when the user has Verilog/SystemVerilog RTL files and wants a quick area or timing estimate without running a full EDA flow, when they mention "fast_elab" or "fast elaboration", or when they want to check logic depth, critical path, or cell statistics of an RTL design.

RTL coding style guide for Verilog/SystemVerilog design. CRITICAL: Load this skill for ANY task involving RTL input/output, including design, implementation, code review, and discussion phases. As soon as you identify a task involves RTL/Verilog/SystemVerilog (e.g., 'design a FIFO', 'create a state machine', 'review this Verilog code'), immediately load this skill. Do NOT wait until code generation phase. RTL coding standards affect design decisions from the very beginning.

Build a verification environment (testbench, testcases, simulation, regression, coverage) for RTL/IP. Default simulator is VCS when no explicit preference is given. Default regression management tool is simforge when no explicit tool is specified. Use this skill whenever the user wants to set up a verification platform, build a testbench, write SystemVerilog testcases, run simulations, manage regressions, or collect/analyze coverage — even if they don't mention a specific tool. Also consult this skill from ip-design Steps 6/7/9/10.

Guide for writing testplan.md for RTL/IP verification. Covers testplan format, testcase naming conventions, TB timing/scheduling rules (driver offset, monitor sampling, cross-clock drain), parameter test matrix, coverage targets, and review checklist. Use this skill whenever writing or reviewing a testplan, defining testcase naming, specifying simulation timing rules, setting coverage targets, or checking testplan completeness for an RTL design.

Read and analyze chip simulation waveform files (VCD/FST/FSDB/GHW) using the wave_reader CLI tool. Use this skill whenever the user mentions waveform files, signal values, simulation debugging, VCD/FST/FSDB/GHW files, timing diagrams, clock analysis, chip verification, or wants to inspect simulation results. Also trigger when you see .vcd, .fst, .fsdb, or .ghw file extensions in the workspace, when the user mentions signal names like clk/reset/valid/ready/data, or when debugging chip-level failures involving timing or signal transitions — even if they don't explicitly say "wave_reader".

Read and analyze chip verification coverage databases (UCIS XML, Synopsys VDB, Cadence UCD, Siemens UCDB) using the cov_reader CLI tool and Python API. Use this skill whenever the user mentions coverage data, coverage reports, coverage holes, uncovered bins, covergroups, line/toggle/branch/condition/FSM/assertion coverage, or wants to inspect verification results. Also trigger when the user mentions waivers, exclusions, .cwv.yaml files, .el files, .vRefine files, coverage filtering, excluding DFT signals, or wants to see "effective coverage" after excluding known gaps. Also trigger when you see .xml (UCIS), .vdb, .ucd, .ucdb file extensions in the workspace, when the user mentions coverage metrics like "line coverage 80%", "toggle coverage", "coverpoint", "cross coverage", or when debugging verification gaps — even if they don't explicitly say "cov_reader".

EDA toolchain configuration and debugging knowledge base. Records configuration, compilation, linking, and version-compatibility issues encountered with VCS, Xrun, Design Compiler, and other EDA tools at the IT infrastructure level (not IC design knowledge). This skill serves as a continuously growing case library — new toolchain issues should always be added here.

Fast RTL PPA analysis using Yosys + OpenSTA. Use this skill whenever the user mentions quick synthesis, gate count estimation, logic depth analysis, flip-flop count, combinational cell count, design hierarchy exploration after synthesis, or fast PPA (Power/Performance/Area) estimation. Also trigger when the user has Verilog/SystemVerilog RTL files and wants a quick area or timing estimate without running a full EDA flow, when they mention "fast_elab" or "fast elaboration", or when they want to check logic depth, critical path, or cell statistics of an RTL design.

Preprocess and flatten hierarchical Verilog/SystemVerilog filelists using the fexpand CLI tool. Use this skill whenever the user mentions filelists, .f files, filelist expansion, -f includes, hierarchical filelists, or wants to preprocess EDA filelists into a flat list. Also trigger when you see .f file extensions, filelist-related commands like +incdir+, -y, -f, or when the user wants to resolve environment variables in filelists, deduplicate file paths, split VHDL files, or expand macros (`ifdef/`endif) in filelists — even if they don't explicitly say "fexpand".

Generate floorplan guide documents and layout diagrams for physical design (PD) teams based on RTL source code analysis. Use this skill whenever the user mentions floorplan, floor plan, FP guide, PD guide, physical design planning, chip layout, macro placement, timing-driven placement, module placement strategy, die floorplan, or asks to analyze RTL for physical implementation. Also trigger when the user wants to create placement constraints, identify critical timing paths for PD, estimate module areas, plan power grid strategy, or produce any deliverable intended for a physical design team — even if they don't explicitly say "floorplan".

Guide for RTL/IP design — new designs from scratch, existing-RTL documentation, or existing-doc implementation. Covers spec-first workflow, user confirmation gates, project structure, RTL/filelist/testbench/testcase/SDC synchronization. Use when user asks to design new IP, write docs for existing RTL, implement RTL from existing docs, add testbenches, or any combination of RTL design deliverables.

Guide for reporting reproducible issues as self-contained compressed archives, and for triaging received issue packages. Use this skill when the user asks to report a bug, file an issue, create a repro case, package a problem for handoff, or whenever you encounter a tool/environment failure that should be escalated. Also use when the user provides a .tar.gz issue package and asks you to investigate, reproduce, or fix it.

RTL coding style guide for writing clean, maintainable Verilog/SystemVerilog. Use this skill whenever the user writes RTL code, asks for code review of hardware designs, wants coding style advice for Verilog/SystemVerilog, or when generating RTL — apply these rules automatically. Triggers include: 'RTL style', 'coding style', 'code review RTL', 'SystemVerilog style', 'Verilog convention', 'naming convention RTL', 'RTL best practice', module definition, signal naming, or any RTL code generation task.

Manage chip verification regression runs using the simforge CLI tool. Use this skill whenever the user wants to submit, monitor, cancel, or analyze regression runs, wants to run simulation testcases in parallel, needs to merge coverage data from multiple simulation runs, asks about testplan YAML, tag-based case filtering, regression status, or failed case analysis — even if they don't explicitly say "simforge".

Retrospective analysis of skill effectiveness after completing a task. Use when user requests skill improvement analysis (e.g., "做skill改善分析", "skill improvement analysis", "analyze skill gaps"). Analyzes the conversation to identify where goals were missed or required excessive iteration, then produces generalized, actionable improvement proposals saved to a structured report.

Use this skill whenever the user wants to lint, analyze, or check SystemVerilog (.sv) design files. Triggers include: any mention of 'SystemVerilog lint', 'SV lint', 'svlinter', 'check RTL', 'check design', 'AST dump', or requests to find errors/warnings in hardware designs. Also use when filtering or querying design instances/modules, dumping syntax trees, or running diagnostics on Verilog/SystemVerilog source files. If the user asks to 'lint my design', 'check my SV files', 'find errors in RTL', or wants to analyze module hierarchies, use this skill.

Use this skill when the user asks to verify that custom tools are installed correctly, run a self-test, check tool availability, or diagnose missing binaries. Triggers include: 'self test', 'self-test', 'check tools', 'verify installation', 'are my tools installed', 'test installation', 'which tools are available', 'tool health check', or any request to confirm that svlinter, terminal_manager, fast_elab, wave_reader, cov_reader, or simforge can be found and executed.

Manage persistent terminal sessions (tmux) using the terminal_manager CLI tool. Use this skill whenever the user needs long-running terminal sessions, EDA tool shells, background processes, or persistent command environments. Trigger when the user mentions terminal management, persistent sessions, tmux, background processes, EDA tool sessions (DC shell, VCS, Innovus), or wants to run commands that need session state persistence — even if they don't explicitly say "terminal_manager".

Read and analyze chip simulation waveform files (VCD/FST/FSDB/GHW) using the wave_reader CLI tool. Use this skill whenever the user mentions waveform files, signal values, simulation debugging, VCD/FST/FSDB/GHW files, timing diagrams, clock analysis, chip verification, or wants to inspect simulation results. Also trigger when you see .vcd, .fst, .fsdb, or .ghw file extensions in the workspace, when the user mentions signal names like clk/reset/valid/ready/data, or when debugging chip-level failures involving timing or signal transitions — even if they don't explicitly say "wave_reader".