القائمة
Generate APB or AHB Verilog register-file RTL from a YAML register description. Use for deterministic register implementation from an approved YAML source.
التثبيت باستخدام Codex أو Claude انسخ هذا Prompt والصقه في Codex أو Claude أو مساعد آخر ليراجع صفحة Skill ويثبّتها لك.
استنادا إلى تصنيف SOC المهني
| name | yml2reg |
| description | Generate APB or AHB Verilog register-file RTL from a YAML register description. Use for deterministic register implementation from an approved YAML source. |
Call the registered yml2reg MCP tool with an existing YAML file and protocol=apb|ahb. Output is written beside the YAML input; failures are MCP tool errors.
Supported access types are rw, ro, wo, w1t, and wc.
Minimal YAML:
name: my_reg
bytes: 4
offset: 0x000
registers:
- name: ctrl_reg
offset: 0x0
fields:
- {name: enable, lsb: 0, bits: 1, access: rw, reset: 0x0}
Review generated bus timing, reset values, address decode, and access semantics before integration. Do not hand-edit generated RTL; change the YAML and regenerate.
Create and operate canonical SoC project/module scaffolds through registered MCP tools for filelists, lint, compile, simulation, regression, coverage, and synthesis. Use for SoC project setup and any EDA Make-target execution.
Close stale multi-stage SoC delivery evidence for a router-selected merge or signoff packet. Use only when vibe-soc-loop delegates final architecture, doc, RTL, verification, synthesis, integration, or PD closure; do not use for ordinary dev iterations.
Route one-sentence vibe_soc feature, RTL, integration, verification, synthesis, register, CRG, low-power, or PD requests into the smallest safe Loop execution packet. Use for SoC work that needs task classification, MCP selection, pipeline state, or delivery closure.
Generate Synopsys .db technology or stub libraries for early synthesis and link. Use when converting Liberty .lib to .db with lc_shell, or when creating a minimal black-box Liberty/.db from a Verilog top module port list.
Prepare and run local-default OpenROAD-flow-scripts physical-design handoff for silicon-crew SoC projects. Use when Codex needs to generate ORFS config/SDC under pd/openroad, run synth/floorplan/place/cts/route/finish/all stages through the default local ORFS path or explicit container backends, summarize OpenROAD reports/results, or connect vibe_soc-style RTL projects to OpenROAD.
Convert reviewed clock/reset Excel design tables into Draw.io and Excalidraw topology diagrams. Use for CRG source, mux, divider, OCC, ICG, and reset-chain visualization.