Assess synthesis-stage ASIC setup and hold timing with backend-independent OpenADA evidence. Use when validating a mapped netlist against a Liberty corner and SDC, reviewing WNS, TNS, unconstrained endpoints and worst setup/hold path summaries, diagnosing whether a timing miss is trustworthy, comparing one controlled timing experiment, or deciding the next closure action without presenting ideal-interconnect static timing as routed or signoff timing.
Assess ASIC synthesis, technology mapping, and inferred hardware with backend-independent OpenADA evidence. Use when reviewing whether RTL produced a complete Liberty-mapped netlist, investigating unexpected register, latch, memory, arithmetic, or mux structures, comparing controlled synthesis experiments, or deciding whether a netlist is trustworthy enough for static timing without confusing successful mapping with functional equivalence or specification closure.
Close analog, mixed-signal, custom-digital, or top-level IC layout through small visually reviewed increments with fresh DRC, LVS, extraction, and performance evidence. Use when editing or debugging GDS, OASIS, Magic, KLayout, or custom-cell layout; placing matched or parasitic-critical devices; routing sensitive nets; repairing DRC or LVS markers; integrating hard macros; or diagnosing geometry that is difficult to understand from text reports alone.
Review ASIC RTL architecture with backend-independent OpenADA lint and structural evidence. Use for SystemVerilog or Verilog design reviews involving hierarchy, clocks and resets, state/control structure, parameterization, inferred latches or combinational loops, arithmetic width, signedness, overflow or saturation diagnostics, interface protocols, or deciding whether RTL is ready for synthesis without treating a clean lint run as functional verification.
Bootstrap and coordinate a fresh open-source ASIC project when the PDK, EDA runtime, project configuration, or physical-design collateral is missing or ambiguous. Use for requests to choose an open PDK, provision compatible tools, create a reproducible ASIC workspace, turn RTL such as a CPU into a core or full-chip tapeout candidate, add an IO/pad ring, or stage-gate synthesis, place-and-route, timing, DRC, LVS, and final handoff without confusing open-tool evidence with foundry signoff.
Analyze, plan, and review backend-independent analog-block behavior and characterization through OpenADA semantic intents. Use for qualitative schematic or topology reasoning, transient-phase and scaling analysis, device-sizing tradeoffs, defining a characterization matrix for an amplifier, regulator, comparator, reference, oscillator, data converter, or other analog block, choosing the next justified analysis, coordinating specialist workflows, or separating simulation evidence from measurements, specification results, and signoff.
Discover, invoke, and interpret open-source EDA tools through OpenADA's versioned CLI contract. Use for semiconductor or electronics work involving Xschem schematics (.sch), SPICE simulation, GDS/KLayout DRC, Netgen LVS, Verilog/SystemVerilog lint, Yosys ASIC synthesis, OpenSTA timing, PDK discovery, or diagnosing an open EDA environment in Codex, Claude Code, or another terminal-capable agent.
Analyze feedback-loop stability with backend-independent OpenADA evidence. Use for differential, common-mode, nested, feed-forward, regulator, or switched-loop questions involving operating-point validity, loop injection and probe identity, gain and phase crossover review, phase or gain margin, closed-loop correlation, oscillation diagnosis, or choosing one focused compensation experiment without relying on simulator-specific commands.