bedrock-rtl

Write or update one Bedrock-RTL SystemVerilog simulation testbench and its Bazel sim target. Use when Codex needs to add, refactor, debug, or review a verilog_sim_test/br_verilog_sim_test_tools_suite bench for VCS or Verilator, including parameterized tests, ready/valid stimulus, scoreboards, and portable smoke/regression coverage that complements formal verification.