vibe_circuit_deisgn.skill

Use when you want to run VCS simulation, DC synthesis, and FM formal verification as a team workflow (serial: VCS → DC → FM). Includes memory checkpoint mechanism for crash recovery.

Use when running Synopsys Design Compiler (DC) synthesis on a remote Linux server. First copy from example template, then modify per design. Covers project setup, constraint writing, synthesis execution, and result analysis.

Use when running Synopsys Formality (FM) formal verification on a remote Linux server. First copy from example template, then modify per design. Covers project setup, SVF integration, execution, and result analysis.

Use when running Cadence Innovus Place & Route on a remote Linux server. Covers project setup, floorplan, CTS, routing, and signoff for TSMC 65nm designs. First copy from example template, then modify per design. Use this skill whenever the user mentions Innovus, P&R, place and route, backend, physical design, GDS generation, or wants to run post-synthesis layout.

Use when developing Verilog/SystemVerilog on a remote Linux server with VCS and viewing waveforms locally in VS Code with VaporView. First copy from example template, then modify per design.