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Formal property verification and model checking skill for FPGA designs
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Reference for querying the Atlas knowledge graph through its MCP tools — the SECONDARY enrichment/comparison layer that adds best-practice context to systems you have ALREADY scanned from your real sources (`az`, repos, dirs). Use when you need to look up nodes, edges, kinds, clusters, stats, or wiki pages in Atlas to compare against your real inventory. (atlas graph, query atlas, atlas mcp, search the graph, graph neighbors, atlas record, atlas kinds, enrichment layer)
Atlas turns your STATED NEED into a real systems atlas by SCANNING your actual sources (Azure via `az`, git repos, local dirs) and process/data mining them, THEN enriching against the Atlas knowledge graph. Use this skill when asked to inventory/map your real systems, scan your cloud + repos + directories, mine the real processes or data they contain, or collect their real constraints/gotchas. (atlas, scan my systems, inventory our azure account, map my repos, real systems atlas, process mining, data mining, collect nuances, system discovery)
This skill should be used when the user asks to "find skills in the wild", "assimilate popular workflows", "discover SKILL.md files in repos", "research external skills", "find workflow patterns", "survey the skill landscape", "what skills exist out there", or wants to investigate public repositories for extractable processes, babysitter plugins, and reusable procedural insights. Searches GitHub for SKILL.md files, classifies repos by archetype, and maintains structured research under docs/reference-repos/.
Based on SOC occupation classification
| name | formal-verification |
| description | Formal property verification and model checking skill for FPGA designs |
| allowed-tools | ["Read","Write","Edit","Glob","Grep","Bash"] |
| graph | {"domains":["domain:embedded-systems"],"specializations":["specialization:fpga-programming"],"skillAreas":["skill-area:hdl-design","skill-area:fpga-synthesis"],"roles":["role:embedded-engineer"]} |
Expert skill for formal property verification and model checking, enabling exhaustive verification of FPGA design properties without simulation.
// Safety property
assert property (@(posedge clk) disable iff (rst)
req |-> ##[1:5] gnt);
// Liveness property (bounded)
assert property (@(posedge clk) disable iff (rst)
req |-> s_eventually gnt);
// Assumption for formal
assume property (@(posedge clk)
$onehot0(req_vec));