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UpdatedJuly 4, 2026 at 13:30

Create a new Buckyball Ball operator named $ARGUMENTS, covering the full flow from implementation to verification.

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DangoSys

DangoSys/buckyball

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Computer Hardware EngineersArchitecture and Engineering Occupations·SOC 17-2061

SKILL.md

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name	ball
description	Create a new Buckyball Ball operator named $ARGUMENTS, covering the full flow from implementation to verification.

Important: all build/simulation operations must go through MCP tools (validate, bbdev_workload_build, bbdev_verilator_run, etc.). Do not use bbdev CLI or nix develop directly.

Phase 1 - Requirement Collection

Inspect registration state and decide ballId + funct7:
- arch/src/main/scala/framework/balldomain/configs/default.json
- examples/chips/toy/arch/src/main/scala/balldomain/DISA.scala
Check for partial existing implementation (incremental mode):
- existing directory in examples/balls/
- existing ISA macro in bb-tests/workloads/lib/bbhw/isa/
- existing CTest in bb-tests/workloads/src/CTest/toy/
Confirm with user:
- operator semantics
- inBW / outBW
- whether op2 is needed
- meaning of iter

Phase 2 - Implement the Ball

Read references:
- simple example: .../prototype/relu/ReluBall.scala, Relu.scala
- complex example: .../prototype/systolicarray/
- Blink protocol: .../blink/blink.scala, bank.scala, status.scala
- SRAM IO: .../memdomain/backend/banks/SramIO.scala
Create files under examples/balls/<name>/arch/src/main/scala/ using templates from references/.

Key constraints

SRAM read latency is 1 cycle (resp.valid in the cycle after req.fire)
Latch command fields when cmdReq.fire
Base FSM pattern: idle -> read -> compute -> write -> complete -> idle
status.idle and status.running must map correctly to FSM states

Phase 3 - Register the Ball

Update files in order:

.../configs/default.json - append ballIdMappings entry and update ballNum
.../bbus/busRegister.scala - add import + match case
.../DISA.scala - add val XXX = BitPat("bxxxxxxx")
.../DomainDecoder.scala - add decode row (BID = ballId.U)

Phase 4 - Add ISA C Macro

Create <funct7_decimal>_<name>.c under bb-tests/workloads/lib/bbhw/isa/, then include it in isa.h.

Phase 5 - Add CTest

Create <name>_test.c under bb-tests/workloads/src/CTest/toy/
Register in bb-tests/workloads/src/CTest/toy/CMakeLists.txt using add_cross_platform_test_target

Phase 6 - Validate, Build, and Simulate

Run validate and ensure all 6 invariants pass
Run bbdev_workload_build
Run bbdev_verilator_run for this Ball's CTest binary
Interpret results:
- PASSED -> done
- FAILED -> switch to /debug

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Verify functional correctness of the Ball named $ARGUMENTS. Use this skill when users ask to verify/test a Ball, check whether a Ball works correctly, or validate a newly created Ball.

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Analyze and optimize latency and area for the RTL module named $ARGUMENTS. Applies to any RTL module (Ball, MemFrontend, BBus, GlobalROB, etc.), not limited to Ball operators.

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Use waveform-mcp tools to analyze VCD/FST waveforms and inspect Buckyball signal timing. Use this skill for cycle-level timing analysis, handshake debugging, FSM transition checks, or whenever waveform-level evidence is needed.

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name	ball
description	Create a new Buckyball Ball operator named $ARGUMENTS, covering the full flow from implementation to verification.

Important: all build/simulation operations must go through MCP tools (validate, bbdev_workload_build, bbdev_verilator_run, etc.). Do not use bbdev CLI or nix develop directly.

Phase 1 - Requirement Collection

Inspect registration state and decide ballId + funct7:
- arch/src/main/scala/framework/balldomain/configs/default.json
- examples/chips/toy/arch/src/main/scala/balldomain/DISA.scala
Check for partial existing implementation (incremental mode):
- existing directory in examples/balls/
- existing ISA macro in bb-tests/workloads/lib/bbhw/isa/
- existing CTest in bb-tests/workloads/src/CTest/toy/
Confirm with user:
- operator semantics
- inBW / outBW
- whether op2 is needed
- meaning of iter

Phase 2 - Implement the Ball

Read references:
- simple example: .../prototype/relu/ReluBall.scala, Relu.scala
- complex example: .../prototype/systolicarray/
- Blink protocol: .../blink/blink.scala, bank.scala, status.scala
- SRAM IO: .../memdomain/backend/banks/SramIO.scala
Create files under examples/balls/<name>/arch/src/main/scala/ using templates from references/.

Key constraints

SRAM read latency is 1 cycle (resp.valid in the cycle after req.fire)
Latch command fields when cmdReq.fire
Base FSM pattern: idle -> read -> compute -> write -> complete -> idle
status.idle and status.running must map correctly to FSM states

Phase 3 - Register the Ball

Update files in order:

.../configs/default.json - append ballIdMappings entry and update ballNum
.../bbus/busRegister.scala - add import + match case
.../DISA.scala - add val XXX = BitPat("bxxxxxxx")
.../DomainDecoder.scala - add decode row (BID = ballId.U)

Phase 4 - Add ISA C Macro

Create <funct7_decimal>_<name>.c under bb-tests/workloads/lib/bbhw/isa/, then include it in isa.h.

Phase 5 - Add CTest

Create <name>_test.c under bb-tests/workloads/src/CTest/toy/
Register in bb-tests/workloads/src/CTest/toy/CMakeLists.txt using add_cross_platform_test_target

Phase 6 - Validate, Build, and Simulate

Run validate and ensure all 6 invariants pass
Run bbdev_workload_build
Run bbdev_verilator_run for this Ball's CTest binary
Interpret results:
- PASSED -> done
- FAILED -> switch to /debug