#001gen-tb-skill1 skills196updated 2026-07-14100% of creatorskilloccupationdescriptionupdatedgen-tbcomputer-hardware-engineers-172061Generate a complete UVM testbench scaffold for a single IP from its spec documents (docx/pdf/md) and register table (xlsx/csv/md/IP-XACT). Use whenever the user asks to "generate a UVM tb", "build a verification environment", "scaffold a testbench", "create a UVC", "set up DV for this IP", or anything equivalent in Chinese ("ๅธฎๆ็ๆ้ช่ฏ็ฏๅข", "ๆญไธไธช tb", "ๅ UVM ็ฏๅข", "ๅ่ฟไธช IP ็้ช่ฏ"). Also trigger when the user points at a directory containing an IP spec and asks Claude to "verify it" / "test it" without naming UVM explicitly. Produces a runnable UVM tb (APB / AHB-Lite / AXI4-Lite as first-class buses; other single-channel buses via a generic fallback) with sanity + register-access tests passing, plus a DE-friendly `tb_api::` task BFM.2026-07-14Showing top 1 of 1 collected skills in this repository.Load 0 more skillsLoading skills...