| name | linx-core |
| description | LinxCore (rtl/LinxCore) development workflow + block/BID/BROB/BISQ design decisions. Use for any LinxCore backend/bctrl work, especially block-structure (BSTART/BSTOP/EOB), BID allocation, and flush semantics. |
Linx Core
Canonical repo location (superproject checkout):
Cross-gate closure (mandatory)
Run these before declaring LinxCore closure:
cmake -S /Users/zhoubot/linx-isa/rtl/LinxCore -B /Users/zhoubot/linx-isa/rtl/LinxCore/build
cmake --build /Users/zhoubot/linx-isa/rtl/LinxCore/build -j"$(sysctl -n hw.ncpu 2>/dev/null || nproc)"
bash /Users/zhoubot/linx-isa/rtl/LinxCore/tests/test_stage_connectivity.sh
bash /Users/zhoubot/linx-isa/rtl/LinxCore/tests/test_runner_protocol.sh
bash /Users/zhoubot/linx-isa/rtl/LinxCore/tests/test_cosim_smoke.sh
bash /Users/zhoubot/linx-isa/rtl/LinxCore/tests/test_opcode_parity.sh
bash /Users/zhoubot/linx-isa/rtl/LinxCore/tests/test_trace_schema_and_mem.sh
bash /Users/zhoubot/linx-isa/rtl/LinxCore/tests/test_rob_bookkeeping.sh
bash /Users/zhoubot/linx-isa/rtl/LinxCore/tests/test_block_struct_pyc_flow.sh
Nightly escalation gates:
bash /Users/zhoubot/linx-isa/rtl/LinxCore/tests/test_coremark_crosscheck_1000.sh
bash /Users/zhoubot/linx-isa/rtl/LinxCore/tests/test_cbstop_inflation_guard.sh
Chisel lane bring-up gates
For the Chisel replacement lane under rtl/LinxCore/chisel, use the repo-local
wrappers rather than invoking sbt directly. The wrappers source
tools/chisel/chisel_env.sh, which prefers Homebrew openjdk@17 when
JAVA_HOME is unset.
Current Phase 0/0B/1/2/5-prep gate sequence:
cd /Users/zhoubot/linx-isa/rtl/LinxCore
bash tools/chisel/build_chisel.sh
bash tools/chisel/run_chisel_tests.sh --only InterfaceBundles
bash tools/chisel/run_chisel_tests.sh --only F4DecodeWindow
bash tools/chisel/run_chisel_tests.sh --only FrontendInstructionBuffer
bash tools/chisel/run_chisel_tests.sh --only FrontendDecodeIngress
bash tools/chisel/run_chisel_tests.sh --only FrontendDecodeStage
bash tools/chisel/run_chisel_tests.sh --only FrontendFetchPacketSource
bash tools/chisel/run_chisel_tests.sh --only ROBID
bash tools/chisel/run_chisel_tests.sh --only ROBEntryStatus
bash tools/chisel/run_chisel_tests.sh --only ROBEntryBank
bash tools/chisel/run_chisel_tests.sh --only ROBFlushPrune
bash tools/chisel/run_chisel_tests.sh --only DispatchROBAllocator
bash tools/chisel/run_chisel_tests.sh --only FullBidRecoveryBridge
bash tools/chisel/run_chisel_tests.sh --only RecoveryCleanupControl
bash tools/chisel/run_chisel_tests.sh --only GPRRenameCheckpoint
bash tools/chisel/run_chisel_tests.sh --only ScalarDecodeRenameBridge
bash tools/chisel/run_chisel_tests.sh --only TULinkRename
bash tools/chisel/run_chisel_tests.sh --only TULinkRelationCmap
bash tools/chisel/run_chisel_tests.sh --only TULinkRetireCommandPath
bash tools/chisel/run_chisel_tests.sh --only TULinkFlushSequencePublisher
bash tools/chisel/run_chisel_tests.sh --only TULinkLocalBlockCommitFanout
bash tools/chisel/run_chisel_tests.sh --only TULinkLocalBankArray
bash tools/chisel/run_chisel_tests.sh --only TULinkRecoveryCleanupPath
bash tools/chisel/run_chisel_tests.sh --only TULinkFlushSourceSelector
bash tools/chisel/run_chisel_tests.sh --only ScalarTURenameBridge
bash tools/chisel/run_chisel_tests.sh --only DecodeLoadStoreIdAssign
bash tools/chisel/run_chisel_tests.sh --only StoreSplitPayload
bash tools/chisel/run_chisel_tests.sh --only StoreDispatchQueues
bash tools/chisel/run_chisel_tests.sh --only StoreDispatchToSTQ
bash tools/chisel/run_chisel_tests.sh --only STQInsertProbe
bash tools/chisel/run_chisel_tests.sh --only StoreDispatchSTQPath
bash tools/chisel/run_chisel_tests.sh --only DecodeRenameQueue
bash tools/chisel/run_chisel_tests.sh --only DecodeRenameROBPath
bash tools/chisel/run_chisel_tests.sh --only STQFlushPrune
bash tools/chisel/run_chisel_tests.sh --only STQEntryBank
bash tools/chisel/run_chisel_tests.sh --only STQCommitQueue
bash tools/chisel/run_chisel_tests.sh --only STQCommitDrain
bash tools/chisel/run_chisel_tests.sh --only SCBCommitIngress
bash tools/chisel/run_chisel_tests.sh --only SCBCommitBridge
bash tools/chisel/run_chisel_tests.sh --only SCBEgressSelect
bash tools/chisel/run_chisel_tests.sh --only SCBLookupControl
bash tools/chisel/run_chisel_tests.sh --only SCBStateUpdate
bash tools/chisel/run_chisel_tests.sh --only SCBRowBank
bash tools/chisel/run_chisel_tests.sh --only SCBResponseDecode
bash tools/chisel/run_chisel_tests.sh --only SCBResponseBuffer
bash tools/chisel/run_chisel_tests.sh --only SCBResponseRetryQueue
bash tools/chisel/run_chisel_tests.sh --only SCBResponseRetrySelect
bash tools/chisel/run_chisel_tests.sh --only STQSCBCommitPath
bash tools/chisel/run_chisel_tests.sh --only MDBConflictDetect
bash tools/chisel/run_chisel_tests.sh --only MDBSSIT
bash tools/chisel/run_chisel_tests.sh --only MDBQueueFanout
bash tools/chisel/run_chisel_tests.sh --only LoadStoreForwarding
bash tools/chisel/run_chisel_tests.sh --only LoadForwardPipeline
bash tools/chisel/run_chisel_tests.sh --only LoadInflightQueue
bash tools/chisel/run_chisel_tests.sh --only LoadReplayWakeup
bash tools/chisel/run_chisel_tests.sh --only LoadRefillWakeup
bash tools/chisel/run_chisel_tests.sh --only CommitTrace
bash tools/chisel/run_chisel_tests.sh --only FlushControl
bash tools/chisel/run_chisel_tests.sh --only BROB
bash tools/chisel/run_chisel_tests.sh --only BrobOrderState
bash tools/chisel/run_chisel_tests.sh --only BrobStoreRangeState
bash tools/chisel/run_chisel_brob_order_state_probe.sh
bash tools/chisel/run_chisel_brob_store_range_state_probe.sh
bash tools/chisel/run_chisel_brob_store_count_publisher_probe.sh
bash tools/chisel/run_chisel_decode_load_store_id_assign_probe.sh
bash tools/chisel/run_chisel_tests.sh --only BlockScalarDoneSequencer
bash tools/chisel/run_chisel_tests.sh --only BlockMarkerLifecycle
bash tools/chisel/run_chisel_tests.sh --only BlockMarkerDecodeContextSpec
bash tools/chisel/run_chisel_tests.sh --only BlockMarkerRetireSourceSerializer
bash tools/chisel/run_chisel_tests.sh --only ReducedCommitROB
bash tools/chisel/run_chisel_tests.sh --only LinxCoreTop
bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendTraceTop
bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchTraceTop
bash tools/chisel/run_chisel_tests.sh --only ReducedScalarAluExecute
bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendAluTraceTop
bash tools/chisel/run_chisel_tests.sh --only ReducedScalarRegisterFile
bash tools/chisel/run_chisel_tests.sh --only ReducedScalarIssueQueue
bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendRfAluTraceTop
bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop
bash tools/chisel/run_chisel_rob_bookkeeping.sh --robid-only
bash tools/chisel/run_chisel_rob_bookkeeping.sh --reduced-rob
bash tools/chisel/run_chisel_reduced_rob_xcheck.sh
bash tools/chisel/run_chisel_top_xcheck.sh
bash tools/chisel/run_chisel_trace_replay_xcheck.sh
bash tools/chisel/run_chisel_frontend_trace_top_lint.sh
bash tools/chisel/run_chisel_frontend_trace_top_xcheck.sh
bash tools/chisel/run_chisel_frontend_fetch_trace_top_xcheck.sh
bash tools/chisel/run_chisel_frontend_alu_trace_top_xcheck.sh
bash tools/chisel/run_chisel_frontend_rf_alu_trace_top_xcheck.sh
bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh
bash tools/chisel/build_frontend_fetch_rf_alu_qemu_fixture_elf.sh --out-dir generated/r100-live-qemu-fixture
bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \
--elf generated/r100-live-qemu-fixture/frontend_fetch_rf_alu_qemu_fixture.elf \
--expected-rows 3 --capture-rows 3 --pc-lo 0x10002 --pc-hi 0x1000b \
--max-seconds 5
bash tools/chisel/run_chisel_verilator_lint.sh
python3 tools/chisel/trace_schema_adapter.py --self-test
bash tools/chisel/run_chisel_qemu_crosscheck.sh --dry-run
bash tools/chisel/run_chisel_qemu_trace_replay_xcheck.sh --dry-run
For any non-dry-run comparison routed through
tools/chisel/run_chisel_qemu_crosscheck.sh, inspect and preserve
<report-dir>/crosscheck_manifest.json with the rest of the evidence bundle.
The manifest records raw traces, normalized traces, comparator reports,
selected QEMU binary, max_commits, normalize_rows, row counts, mismatch
summary, CBSTOP summary, and LinxCore/superproject git context. The wrapper
must still emit the manifest on comparator failure and then return the
comparator status.
Generated-RTL Verilator harnesses must emit commit JSONL through
tools/chisel/commit_trace_jsonl.h rather than open-coded per-harness JSON
strings. The helper owns QEMU-shaped architectural fields and DUT sidebands
(valid, seq/cycle/slot, bid/gid/rid, ROB id, and block_bid); harnesses
own only top-specific pin conversion. This preserves model CommitInfo
identity separately from the BID_W-bit hardware block BID and prevents
schema drift before live Chisel trace writers are added.
For QEMU trace replay, keep raw replay/normalization depth separate from the
architectural compare depth: QEMU metadata rows may be filtered before compare,
so run_chisel_qemu_trace_replay_xcheck.sh normalizes a wider raw window and
slices the replay input to the smallest prefix containing the requested
non-metadata commits.
Every tools/qemu/run_qemu_commit_trace.sh --max-seconds N invocation must be
a real wall-clock bound. The runner uses timeout/gtimeout when present and
otherwise its Python process-group fallback; a timeout returns 124 after
terminating QEMU. Do not treat a host without GNU coreutils as permission to
run an unbounded CoreMark/QEMU capture.
For PC-filtered QEMU-only preflights that are candidates for generated-RTL
promotion, exact memory-PC guards are necessary but not sufficient. The reduced
preview must also prove that the Verilator harness can reconstruct starting
architectural register state, for example through
state_seed_audit.status="ready" in
tools/chisel/search_replay_liq_pc_filter_preflights.py schema v2. If the
first non-skipped reduced row has memory/destination data but no visible source
operands, treat the PC filter as generated-RTL blocked even when QEMU-only
memory-PC guards pass; the DUT would otherwise start from reset/RF defaults
while QEMU already executed hidden predecessor state. That blocked state can be
reopened only by citing a matching raw-prefix RF seed artifact, for example
one built with tools/chisel/build_frontend_fetch_rf_seed.py from the
unfiltered QEMU trace and passed to generated RTL through --rf-seed /
FETCH_RF_SEED. A seeded comparator pass proves launch-state reconstruction
only; replay-LIQ replacement proof still needs nonzero eligible-store,
ResolveQ, MDB, LIQ allocation, replay-output, and row-mutation counters.
In --elf mode, --replay-rows is also the raw FIFO capture cap. The wrapper
must kill the prefix reader and fail with an empty-trace error if QEMU exits
before producing rows; do not leave agents blocked on a FIFO. Direct-boot
CoreMark-style ET_DYN images currently map load segments at 0x40000000,
while the Linx QEMU virt machine defaults to 128 MiB of RAM. Use trailing
QEMU args with explicit memory for that class of replay, for example:
bash tools/chisel/run_chisel_qemu_trace_replay_xcheck.sh \
--elf tests/benchmarks/build/coremark_real.elf \
--max-commits 4 \
--replay-rows 128 \
--max-seconds 10 \
-- -nographic -monitor none -machine virt -m 1280M \
-kernel tests/benchmarks/build/coremark_real.elf
Chisel module agent loop
Use rtl/LinxCore/docs/chisel/agent-loop.md as the operational runbook for
multi-agent Chisel development. Each module packet must:
- record current
rtl/LinxCore and tools/LinxCoreModel SHAs before edits;
- learn behavior from LinxCoreModel C++ owner files before writing Chisel;
- update the module Markdown spec before promotion;
- for scalar LSU sizing changes, keep three independent domains explicit:
physical queue/storage capacity (
stqEntries, commitQueueEntries,
scbEntries, LIQ/ResolveQ/MDB depths), ROB slot-plus-wrap identity
(robEntries for BID/GID/RID), and full memory-order identity
(lsidWidth, normally 32). Never derive one domain from another. Add at
least one unequal-capacity elaboration, such as 16 STQ rows with 8 ROB
entries and a 40-bit LSID, and assert physical index/mask, ROB identity, and
LSID widths independently;
- keep ROB/commit/flush/BROB/QEMU cross-check infrastructure as the first proof
surface for replacement evidence;
- For BROB non-flush promotion, publish an exact per-STID
(head BID, prefix count) window. An unsafe head, stale slot, hole, or exception must
produce no authorization, and consumers must not use the youngest safe BID
as an unsigned threshold. A store commit retained while waiting for this
proof must carry STID, full block BID, and instruction identity, clear on the
same accepted recovery as STQ/BROB state, and pass both the BROB rollover
probe and run_chisel_store_non_flush_gate_probe.sh before promotion.
- run the narrow module gate plus affected cross-check gates;
- inspect
crosscheck_manifest.json for every generated-RTL or QEMU/DUT
comparison that routes through the common cross-check wrapper; R151 and later
manifests must include git.linxcore, git.linxcore_model, git.qemu, and
git.superproject before the run is cited as replacement evidence;
- for QEMU row replay, verify the reported
qemu-replay-raw-rows and
qemu-replay-arch-rows before treating the manifest as evidence;
- for CoreMark or other direct-boot benchmark ELF replay, pass explicit QEMU
memory if the ELF program headers map above the default 128 MiB RAM window;
- for replay-LIQ MDB promotion, do not claim conflict record or fanout
evidence from aggregate store-probe and ResolveQ counters. Prove a same-cycle
store-detect/ResolveQ overlap, or a model-equivalent retained/replayed store
probe, and require nonzero
mdb_conflict_valid, mdb_fanout_record_*,
BMDB, and SSIT counters while keeping unrelated lookup/wait-plan counters
explicitly guarded;
- for replay-wake promotion, do not treat top-local sideband counters as proof
that the LIQ child consumed a wake when child clear masks disagree. Inspect
final top assignment order and tie-off helpers for the actual
ReducedLoadReplayLiqAllocPath.io.replayWake* inputs before changing
LoadReplayWakeup predicate logic;
- for reduced BFU body-cut work after R153, do not arm body cuts from static
boundary geometry alone. A conditional
BSTART can close the previous model
body but still fall through at runtime, so cut-eligible prediction must come
from accepted resolved body-end evidence or the local window trained by that
evidence. Use the resolved body-end row as the same-cycle cold-cut fallback
because ReducedBfuGeometryPredictionLatch is registered. Keep
ReducedBfuBodyCutArm as diagnostic/oracle comparison until a real
branch/BFU resolver replaces the external replay source. Drive local
body-window D1 scans from registered F4/IB entry validity rather than source out-fire
to avoid body-cut/source-advance combinational cycles;
- close with
skill-evolve: update ... or skill-evolve: no-update ....
Do not treat a frontend/backend Chisel module as replacement evidence merely
because its unit test passes. It needs monitored commit/stage-owner visibility
through the neutral cross-check path before it can displace pyCircuit evidence.
Chisel speed loop
Use this abbreviated loop before opening the full packet ledger. It exists to
avoid repeating the long-session pattern of rereading every historical R packet,
rerunning broad status checks, and rediscovering toolchain facts.
- Read
rtl/LinxCore/docs/chisel/integrated-development-flow.md first, then
only rtl/LinxCore/docs/chisel/development-loop.md, the assigned module
spec, and the latest relevant rows in
rtl/LinxCore/docs/chisel/agent-loop.md.
- Record the four SHAs once: superproject,
rtl/LinxCore,
tools/LinxCoreModel, and emulator/qemu. Do not run repeated git status
checks inside the same packet unless an edit, fetch, commit, or generated
artifact changes the state.
- Validate the Chisel environment once with the repo wrappers. Reuse
tools/chisel/chisel_env.sh; do not call raw sbt from ad hoc working
directories.
- Run gates in tiers from the integrated flow: module unit gate first,
adjacent owner gate second, generated-RTL/QEMU cross-check third, model or
workload promotion fourth, full closure only at promotion.
- For QEMU/DUT failures, stop at the first divergent architectural row and
classify ownership before editing:
chisel, qemu, model, compiler,
adapter, benchmark, or unknown.
- Update the module doc, gate evidence, and ledger in the same packet. If the
finding is reusable across modules, update this skill once; otherwise close
with
skill-evolve: no-update.
- After generated-RTL/QEMU evidence is captured, prune reproducible build
intermediates before starting another broad sweep. Preserve report JSON,
manifests, sideband stats, and trace snippets cited by docs, but remove
generated/**/obj_dir, generated Verilog trees that wrappers can recreate,
wave dumps, and compiler temporaries (*.tmp, *.o, *.a, *.d, *.gch).
If an active generated-RTL run is producing large intermediates and the loop
pivots, terminate that run cleanly before deleting its incomplete build dir.
Prefer bounded evidence windows while debugging. Scale CoreMark or direct-boot
windows only after the narrow module gate and the previous smaller cross-check
pass. Full cross-gate closure remains mandatory before claiming LinxCore
closure, but it is not the inner edit loop.
Toolchain facts from initial Chisel bring-up:
Compatibility terminology: historical Chisel module/test names such as
F4DecodeWindow remain literal code identifiers. In the bring-up notes below,
an "F4 slot/window" means a D1 decode slot/view read from F4/IB state; it never
defines a separate F4 decode stage.
- Homebrew
openjdk@17 works with the wrappers.
- Homebrew
sbt 2.0.0 works when the project uses Scala 2.13.17.
- Chisel is pinned to
7.3.0 in chisel/build.sbt.
- Phase 1 common interface work must run
bash tools/chisel/run_chisel_tests.sh --only InterfaceBundles before
frontend/decode/rename/LSU/ROB agents consume the shared bundle packet.
InterfaceBundles preserves the 4-wide/64-bit pyCircuit widths, 12-bit
opcode, 4-bit instruction length fields, 6-bit reg/ptag/ROB index defaults,
32-bit scalar LSID, BK_* order,
REG_INVALID=0x3f, TRAP_BRU_RECOVERY_NOT_BSTART=0x0000b001, and the split
between model bid/gid/rid identity and hardware blockBid. The current
fixed 64-bit blockBid bundle is legacy implementation shape: new contract
work uses BID_W, and a width migration must update all producers,
consumers, traces, and fixtures coherently.
- Phase 2
F4DecodeWindow is a legacy module name for a D1 decode-window
helper; it is not architectural F4. Work on it must preserve LinxCoreModel CheckMInstSize
instruction sizing: bit 0 clear gives 2 bytes unless header bits [3:1] are
111, which gives 6 bytes; bit 0 set gives 4 bytes unless header bits
[3:1] are 111, which gives 8 bytes. The Chisel gate is
bash tools/chisel/run_chisel_tests.sh --only F4DecodeWindow.
- Legacy decode-window/D1 work must keep 8-byte window slicing sequential and
non-compacting: a candidate that does not fit invalidates that slot and all
later slots; do not search forward for a later instruction. Flush masks D1
and all slot-valid bits. Slot UIDs are
(pktUid << 3) | slot.
- Full opcode decode, register/immediate extraction, macro-boundary standalone
behavior, and D1/D2 uop construction are deferred until the Chisel opcode
table/decode-owner modules exist; do not bury those behaviors in the legacy
F4DecodeWindow transport helper.
- Phase 2
FrontendInstructionBuffer work must run
bash tools/chisel/run_chisel_tests.sh --only FrontendInstructionBuffer.
The buffer is a frontend-owned FIFO for FrontendDecodePacket records:
preserve FIFO order, clear occupancy on flush, keep simultaneous push/pop
occupancy stable, and keep full-state backpressure based on pre-cycle
occupancy.
- Chisel frontend buffers must carry
checkpointId as packet-owned state
alongside PC/window/packet UID. Do not reconstruct F4/IB-to-D1 packet checkpoint
identity from adjacent control wiring once a packet enters the Chisel
frontend queue.
- Phase 2
FrontendDecodeIngress work must run
bash tools/chisel/run_chisel_tests.sh --only FrontendDecodeIngress.
Architecturally this is the F4/IB-to-D1 transport boundary: F4 is the fourth
fetch stage and the instruction-buffer boundary, not a four-slot decode
stage. The current implementation composes
FrontendInstructionBuffer with F4DecodeWindow, pop only on
decodeReady && f4.d1.valid, preserve no same-cycle push-to-D1 bypass,
clear/mask both children on flush, and keep opcode decode, macro-boundary
decode, and D1/D2 uop construction in later decode-owner modules.
- Phase 2/R39/R40
FrontendDecodeStage work must run
bash tools/chisel/run_chisel_tests.sh --only FrontendDecodeStage plus the
affected F4DecodeWindow, FrontendDecodeIngress, and InterfaceBundles
gates. This module is the first D1 decode-shape owner after F4/IB: use the
generated pyCircuit opcode metadata mask/match table, preserve the
most-specific-mask rule (decode16_meta/decode32_meta/decode48_meta/
decode64_meta), emit DecodedUop records with slot PC/raw/len/opcode and
UID/checkpoint identity, and expose block/load/store sideband masks. R40 adds
FrontendOperandDecode as the scalar field owner behind this stage: it
consumes generated rdKind/rs1Kind/rs2Kind/immKind, emits reg6
architectural GPR source/destination tags in pyCircuit srcl/srcr/srcp
order, and forms the common scalar immediates already covered by
src/common/decode.py. Keep LSID allocation, D2 queueing, block header
mutation, store split rewrite, T/U/SGPR/tile/vector operand classes,
shift/source-type sidebands, and rename/ROB admission in later owners.
- Phase 5/R41
ScalarDecodeRenameBridge work must run
bash tools/chisel/run_chisel_tests.sh --only ScalarDecodeRenameBridge plus
affected GPRRenameCheckpoint, FrontendDecodeStage,
DispatchROBAllocator, and reduced ROB bookkeeping gates. This bridge is
the first D2 decode-to-rename staging owner: consume one DecodedUop, map
scalar GPR sources through GPRRenameCheckpoint, optionally allocate one
scalar GPR destination, emit a RenamedUop, and emit the matching
CommitTraceRow allocation request for ROB/BROB allocation. Keep
dec_ren_q registration, width-wide rename, automatic isLastInBlock
checkpoint capture, ready-table initialization, LSID allocation, store split
rewrite, T/U/SGPR/tile/vector rename, live top wiring, and commit side
effects in later owners. The bridge must reject any non-scalar-GPR operand
class or destination kind; FrontendRegAliasClassify is the decode owner
that maps reg6 aliases outside the 24-entry model GPR namespace before the
bridge sees them.
- Phase 5/R42
DecodeRenameROBPath work must run
bash tools/chisel/run_chisel_tests.sh --only DecodeRenameROBPath plus
affected ScalarDecodeRenameBridge, FrontendDecodeStage,
DispatchROBAllocator, GPRRenameCheckpoint, reduced ROB bookkeeping, top
xcheck, and run_chisel_qemu_crosscheck.sh --dry-run gates. This path is
the first reduced frontend/backend composition owner: connect
FrontendDecodeStage, ScalarDecodeRenameBridge, and
DispatchROBAllocator; select one decoded slot; stamp temporary backend
identity from allocator cursors before rename; and allocate a real BROB/ROB
row. When composing with DispatchROBAllocator, drive allocator
allocValid from ScalarDecodeRenameBridge.robAllocAttemptValid, not from
the accepted allocation event, so ROB duplicate-identity ready calculation
sees a stable request row without feeding allocator ready back into
allocator valid. R44 adds the registered dec_ren_q owner, R45 adds the
reduced memory-order ID owner, R46 adds the renamed store payload split
owner, and R47 connects generated store metadata plus reduced store-dispatch
handoff; keep width-wide rename, enqueue-time ROB reservation, full
load_id/sid payload carry, STA/STD execution, STQ mutation, automatic
checkpoint capture, ready-table initialization,
T/U/SGPR/tile/vector operands, full block retire, and live top-level commit
rows in later owner packets.
- Phase 5/R43
FrontendRegAliasClassify / FrontendOperandDecode work must
run bash tools/chisel/run_chisel_tests.sh --only FrontendDecodeStage plus
affected ScalarDecodeRenameBridge, DecodeRenameROBPath, top xcheck,
run_chisel_qemu_crosscheck.sh --dry-run, build_chisel.sh, and
run_chisel_verilator_lint.sh gates. This owner preserves the model scalar
reg6 alias contract: source tags 0..23 are OperandClass.P, 24..27 are
OperandClass.T, 28..31 are OperandClass.U; destination tags 0..23
are DestinationKind.Gpr, tag 31 is the T queue, and tag 30 is the U
queue. Destination aliases intentionally do not use the source T/U ranges.
Keep T/U queue consumption, SGPR/tile/vector operands, LSID/SID allocation,
store split, and full enqueue-time ROB reservation in later owners.
- Phase 5/R44
DecodeRenameQueue / DecodeRenameROBPath work must run
bash tools/chisel/run_chisel_tests.sh --only DecodeRenameQueue plus
affected DecodeRenameROBPath, ScalarDecodeRenameBridge,
FrontendDecodeStage, DispatchROBAllocator, reduced ROB bookkeeping, top
xcheck, run_chisel_qemu_crosscheck.sh --dry-run, build_chisel.sh, and
run_chisel_verilator_lint.sh gates. DecodeRenameQueue is the registered
raw decoded-uop boundary corresponding to model dec_ren_q: enqueue raw
DecodedUop payloads, expose queue push/pop and occupancy observability,
clear on frontend/backend recovery cleanup in the reduced path, and pop only
when scalar rename plus ROB allocation accept. Until an enqueue-time ROB
reservation owner exists, stamp allocator BID/RID identity at the queue head
before ScalarDecodeRenameBridge; do not stamp or reserve allocator cursors
for multiple queued rows at enqueue because that duplicates identities. Later
top-level frontend integration must advance D1 and consume F4/IB only on decodeReady /
queue acceptance.
- Phase 5/R45
DecodeLoadStoreIdAssign / DecodeRenameROBPath work must run
bash tools/chisel/run_chisel_tests.sh --only DecodeLoadStoreIdAssign plus
affected DecodeRenameROBPath, DecodeRenameQueue,
ScalarDecodeRenameBridge, FrontendDecodeStage,
DispatchROBAllocator, reduced ROB bookkeeping, top xcheck,
run_chisel_qemu_crosscheck.sh --dry-run, build_chisel.sh, and
run_chisel_verilator_lint.sh gates. DecodeLoadStoreIdAssign is the first
reduced STID0 memory-order ID owner after frontend decode: stamp the
selected decoded load/store/DCZVA row with the pre-increment 32-bit lsID
only when DecodeRenameQueue accepts the row, expose 64-bit load_id and
sid serial-counter observability, and clear/restore counters through the
recovery hook. This owner may expose storeSplitIntent, but must not clone
STA/STD rows, rewrite PCR store sources, carry load_id/sid through common
uop bundles, or perform width-wide same-cycle slot-order allocation. R46/R47
consume the split intent plus opcode-derived pair/cache/PCR metadata in the
store payload handoff; real store queue mutation remains a later owner.
- Phase 5/R46
StoreSplitPayload work must run
bash tools/chisel/run_chisel_tests.sh --only StoreSplitPayload plus
affected InterfaceBundles, DecodeLoadStoreIdAssign,
ScalarDecodeRenameBridge, DecodeRenameROBPath, DecodeRenameQueue,
FrontendDecodeStage, DispatchROBAllocator, reduced ROB bookkeeping, top
xcheck, run_chisel_qemu_crosscheck.sh --dry-run, build_chisel.sh, and
run_chisel_verilator_lint.sh gates. StoreSplitPayload consumes renamed
store rows carrying storeSplitIntent, pair/cache-maintain suppression, and
PCR metadata. Split stores must fire STA and STD atomically with shared
bid/gid/rid/blockBid/lsid identity; ordinary STA payloads zero source 0;
PCR STA payloads preserve source 0 and use store data source index 1; pair
and cache-maintain stores remain single ST_ALL payloads. This owner must
not allocate or mutate STQ/SCB/MDB state. R47 integrates it behind the
reduced decode/rename/ROB path for payload observability only; R48 adds the
finite STA/STD dispatch queues, while STA/STD execution and STQ residency
remain later owners.
- Phase 5/R47 generated store metadata / reduced store-dispatch handoff work
must run
sbt --client --error 'Test / compile' plus affected
FrontendDecodeStage, DecodeLoadStoreIdAssign, StoreSplitPayload,
ScalarDecodeRenameBridge, DecodeRenameROBPath, DecodeRenameQueue,
InterfaceBundles, DispatchROBAllocator, reduced ROB bookkeeping, top
xcheck, run_chisel_qemu_crosscheck.sh --dry-run, build_chisel.sh, and
run_chisel_verilator_lint.sh gates. Generated decode metadata now drives
load/store-pair, PCR-store, and cache-maintain split sidebands into the
reduced path. When connecting StoreSplitPayload behind scalar rename, compute
store-dispatch readiness from the queued decoded row, not from
StoreSplitPayload.inReady or the accepted renamed output. Unsplit stores
require only STA readiness; split stores require both STA and STD readiness;
gate ScalarDecodeRenameBridge.outReady with that readiness plus downstream
renamed-output readiness. StoreSplitPayload consumes only the accepted
renamed row and emits STA/STD/ST_ALL payload observability. Do not create a
ready/valid loop through the splitter, and do not allocate or mutate
STQ/SCB/MDB state in this reduced path.
- Phase 5/R48
StoreDispatchQueues / queue-backed store-dispatch handoff work
must run sbt --client --error 'Test / compile' plus affected
StoreDispatchQueues, DecodeRenameROBPath, StoreSplitPayload,
DecodeLoadStoreIdAssign, ScalarDecodeRenameBridge, DecodeRenameQueue,
STQEntryBank, InterfaceBundles, DispatchROBAllocator, reduced ROB
bookkeeping, top xcheck, run_chisel_qemu_crosscheck.sh --dry-run,
build_chisel.sh, and run_chisel_verilator_lint.sh gates.
StoreDispatchQueues is the finite queue owner for the model
pe_iex_sta_array/pe_iex_std_array dispatch boundary behind scalar
rename. Its staReady and stdReady are capacity-only and flush-qualified;
they must not depend on staIn/stdIn/unsplitIn.valid or on protocol-error
diagnostics, because those payload-valid bits are produced by
StoreSplitPayload from accepted rename output. Protocol-shape errors must
remain observable and suppress enqueue, but not feed upstream readiness.
Split stores enqueue STA and STD atomically or enqueue neither; unsplit
stores enqueue only the STA-side ST_ALL queue. Do not compute address/data,
allocate STQ rows, or mutate STQ/SCB/MDB state in this queue owner. Future
store-execution packets must consume queue heads and build executed STQ
insert requests rather than moving queue or STQ state back into rename.
- Phase 5/R49
StoreDispatchToSTQ request-bridge work must run
sbt --client --error 'Test / compile' plus affected
StoreDispatchToSTQ, StoreDispatchQueues, STQEntryBank,
StoreSplitPayload, DecodeRenameROBPath, InterfaceBundles, reduced ROB
bookkeeping, top xcheck, run_chisel_qemu_crosscheck.sh --dry-run,
build_chisel.sh, and run_chisel_verilator_lint.sh gates.
StoreDispatchToSTQ consumes queue heads only after explicit STA/STD
execution results are valid and forms typed STQStoreRequest rows. It must
keep address generation and store-data selection outside the bridge. When
both executed candidates can insert, STA wins, matching the model's STA
phase before STD phase. If a present STA candidate cannot insert but the STD
candidate can insert, STD must be allowed to bypass; this preserves the model
progress case where a full STQ rejects a new address allocation while still
accepting a complementary data half merge. Do not force the R48 atomic
rename-time split pair to enter STQ atomically. R61 makes this bridge a
preservation owner for row-owned T/U sidecars: copy tSeq/uSeq and
tuDst* from StoreSplitIssuePayload into STQStoreRequest; do not
re-disable those fields in the bridge.
- Phase 5/R50
STQInsertProbe / StoreDispatchSTQPath work must run
sbt --client --error 'Test / compile' plus affected STQInsertProbe,
StoreDispatchSTQPath, StoreDispatchToSTQ, StoreDispatchQueues,
STQEntryBank, StoreSplitPayload, DecodeRenameROBPath,
InterfaceBundles, reduced ROB bookkeeping, top xcheck,
run_chisel_qemu_crosscheck.sh --dry-run, build_chisel.sh, and
run_chisel_verilator_lint.sh gates. STQInsertProbe is the shared
read-only STQ insert-readiness predicate over the live STQEntryBank row
image, and STQEntryBank must use the same predicate internally. Full
queue-to-STQ composition must compute STA and STD insert readiness with
independent probes before selecting a request; do not feed a selected-only
STQEntryBank.insertReady shortcut back into both candidates. STA still
wins when both executed candidates are ready, but a mergeable STD must be
allowed to bypass a present STA that cannot allocate into a full STQ.
Address generation, store-data selection, load-conflict probes, ready-table
updates, memory trace side effects, and live top integration remain later
owners.
- Phase 5/R51
TULinkRename work must run
sbt --client --error 'Test / compile' plus affected TULinkRename,
FrontendDecodeStage, ScalarDecodeRenameBridge, DecodeRenameROBPath,
and reduced ROB bookkeeping gates. TULinkRename is a standalone scalar T/U
local-register rename owner, not an extension of scalar GPR rename. Preserve
the model LocalRegMgr contract for OPD_TLINK and OPD_ULINK: capture
tSeq/uSeq from mapQAllocPtr[0] before destination allocation; resolve
sources from mapQAllocPtr[0] - (offset + 1) using the frontend T/U
relative tag; allocate destinations from the circular scalar local
allocPtr[0]; and stall on usedEntrySize[0] + 1 > mapSize or
usedPSize[0] + 1 > pSize. Do not use the scalar GPR first-free physical
tag policy for T/U queues. Keep T/U release, ready-table mutation, flush
cleanup, multi-PE/thread banking, and unified renamed-uop composition in
later owner packets.
- Phase 5/R52
TULinkRename cleanup work must run
sbt --client --error 'Test / compile' plus affected TULinkRename,
FlushControl, RecoveryCleanupControl, ScalarDecodeRenameBridge, and
reduced ROB bookkeeping gates. T/U cleanup must preserve the scalar
LocalRegMgr split between marking a row retired and freeing it: plain
ReportRetired(seq, false) only marks the mapQ row, direct dealloc release
may free only the current deallocation head, and ReportBlockCommit(bid)
releases only consecutive retired rows at the deallocation head with matching
BID. Flush pruning for non-base requests must use both local mapQ sequence
and RID ordering:
(flush.bid, localSeq) <= (row.bid, row.seq) and
(flush.bid, flush.rid) <= (row.bid, row.rid). When the flushed instruction
itself owns a T/U destination, the recovery publisher must supply the
previous local sequence, matching model GetPrevRegSeq; do not infer this
from ROB RID alone. Keep the shared ROB/LSU sequence publisher,
relation-cmap release policy, ready-table mutation, and unified renamed-uop
composition in later owner packets.
- Phase 5/R53
TULinkFlushSequencePublisher work must run
sbt --client --error 'Test / compile' plus affected
TULinkFlushSequencePublisher, TULinkRename,
RecoveryCleanupControl, FlushControl, and reduced ROB bookkeeping gates.
The publisher must treat T/U local-register cleanup as a backend PE cleanup
sideband, not scalar stack-rename cleanup: drive commands from
RecoveryCleanupIntent.backendFlushValid plus the selected ROB/LSU row
snapshot. Non-base cleanup requires that source row to match
(flush.bid, flush.rid, flush.stid) and must report/suppress
missing or mismatched sources rather than defaulting the local sequence. Apply
the model GetPrevRegSeq adjustment only for the destination class owned by
the flushed row: T destinations decrement only tSeq, U destinations
decrement only uSeq. Keep live row-snapshot wiring into the cleanup path,
relation-cmap release policy, ready-table
mutation, and multi-PE/thread banking in later owner packets.
- Phase 5/R54
TULinkRecoveryCleanupPath work must run
sbt --client --error 'Test / compile' plus affected
TULinkRecoveryCleanupPath, TULinkFlushSequencePublisher,
TULinkRename, RecoveryCleanupControl, FlushControl, and reduced ROB
bookkeeping gates. The composition must wire publisher outputs directly into
TULinkRename.flush* while keeping live ROB/LSU row selection behind an
explicit flushSource input. If a non-base T/U cleanup is active but the
selected row source is missing or mismatched, treat that as a recovery
barrier: block local T/U rename, retire, and commit for the cycle instead of
falling through to unrelated local-register maintenance. Keep
relation-cmap release policy, ready-table mutation, and multi-PE/thread
banking in later owner packets.
- Phase 5/R55
TULinkFlushSourceSelector work must run
sbt --client --error 'Test / compile' plus affected
TULinkFlushSourceSelector, TULinkRecoveryCleanupPath,
TULinkFlushSequencePublisher, RecoveryCleanupControl, FlushControl,
reduced ROB bookkeeping, trace-schema self-test, and Chisel QEMU dry-run
gates. The selector is the ROB/LSU source-selection boundary for T/U cleanup
sidebands; it is not the live row-storage owner. Non-base cleanup candidates
match by (flush.bid, flush.rid, flush.stid), while base-on-BID cleanup does
not require a selected row source. If ROB and LSU both match the same
non-base cleanup row, their payloads must agree exactly; otherwise suppress
the selected source and let the recovery barrier block local T/U rename,
retire, and commit for the cycle. Keep relation-cmap release policy,
ready-table mutation, and multi-PE/thread banking in later owner packets.
- Phase 5/R56
ROBEntryBank T/U source-sidecar work must run
sbt --client --error 'Test / compile' plus affected InterfaceBundles,
ROBEntryBank, DispatchROBAllocator, DecodeRenameROBPath,
TULinkFlushSourceSelector, TULinkRecoveryCleanupPath,
TULinkFlushSequencePublisher, RecoveryCleanupControl, FlushControl,
reduced ROB bookkeeping, trace-schema self-test, and Chisel QEMU dry-run
gates. The row owner must store stid, row-owned tSeq/uSeq, and
T/U destination class at allocation, then publish robTULinkSource only for
an exact non-base (flush.bid, flush.rid, flush.stid) match. Base-on-BID
cleanup must publish no local sequence source. The source payload must come
from row sidecars captured from the rename snapshot, not from
CommitTraceRow.identity, row index, or default zero sequences. Flush and
deallocation must clear the sidecars with the row. DispatchROBAllocator
forwards these sidecars, and reduced DecodeRenameROBPath now drives them
from ScalarTURenameBridge live SPERename-equivalent snapshots before
T/U destination rename. Keep LSU/STQ source sidecars, selector-to-cleanup
composition, relation-cmap release policy, ready-table mutation, and
multi-PE/thread banking in later owner packets.
- Phase 5/R58
STQEntryBank LSU T/U source-sidecar work must run
sbt --client --error 'Test / compile' plus affected STQEntryBank,
STQFlushPrune, StoreDispatchToSTQ, StoreDispatchSTQPath,
STQInsertProbe, STQCommitDrain, STQSCBCommitPath,
TULinkFlushSourceSelector, TULinkRecoveryCleanupPath, reduced ROB
bookkeeping, trace-schema self-test, and Chisel QEMU dry-run gates. The STQ
request and row owners must carry the model MemReqBus tSeq/uSeq sidecars
plus T/U destination ownership, then publish lsuTULinkSource only for an
exact non-base (flush.bid, flush.rid, flush.stid) row match. Keep this
source separate from STQFlushPrune, whose pruning predicate remains the
model LSU (bid, lsId) recovery rule. Split-store merge must preserve the
first row's T/U source sidecars while filling address/data readiness, matching
STQ::mergeStore and STQueueEntryInfo::init; do not overwrite them from a
later complementary half. StoreDispatchToSTQ must preserve sidecars from
StoreSplitIssuePayload; the reduced backend now drives live payload
sidecar inputs from ScalarTURenameBridge.
Keep relation-cmap release policy, ready-table mutation, and
multi-PE/thread banking in later owner packets.
- Phase 5/R59
DecodeRenameROBPath reduced T/U cleanup source-composition
work must run sbt --client --error 'Test / compile' plus affected
DecodeRenameROBPath, TULinkRecoveryCleanupPath,
TULinkFlushSourceSelector, DispatchROBAllocator, StoreDispatchSTQPath,
reduced ROB bookkeeping, trace-schema self-test, and Chisel QEMU dry-run
gates. The reduced backend may instantiate TULinkRecoveryCleanupPath as a
diagnostic composition point with rename, retire, and commit inputs tied
inactive until scalar and T/U rename state are merged. Drive
TULinkRecoveryCleanupPath.robSource from
DispatchROBAllocator.robTULinkSource and expose an external
lsuTULinkSource input for the future STQ wrapper producer. The emitted
diagnostics must prove whether ROB and LSU candidates agree for the same
(bid,rid,stid), whether one matching source was selected, or whether
cleanup was blocked by a missing or conflicting source. R62 moves this
diagnostic-only owner into ScalarTURenameBridge; do not reintroduce a
second independent T/U cleanup state owner in DecodeRenameROBPath.
- Phase 5/R60
DecodeRenameROBPath integrated STQ-bank LSU source work must
run sbt --client --error 'Test / compile' plus affected
DecodeRenameROBPath, StoreDispatchSTQPath, StoreDispatchToSTQ,
STQEntryBank, TULinkRecoveryCleanupPath, TULinkFlushSourceSelector,
DispatchROBAllocator, reduced ROB bookkeeping, trace-schema self-test,
Chisel QEMU dry-run, and top xcheck gates. The reduced backend may replace
its internal StoreDispatchQueues shell with StoreDispatchSTQPath only if
queue flush and STQ recovery flush remain separate: frontend/decode
maintenance may clear dispatch queues through a queue-only flush, but must
not become an STQ row-prune event. Drive
TULinkRecoveryCleanupPath.lsuSource from the live
StoreDispatchSTQPath.lsuTULinkSource output, and expose enough STQ insert,
occupancy, flush, and source diagnostics to prove the source came from the
STQ bank. R62 moves the cleanup path under ScalarTURenameBridge, where the
publisher outputs mutate live T/U rename state.
- Phase 5/R61 store-dispatch T/U sidecar carry work must run
sbt --client --error 'Test / compile' plus affected StoreSplitPayload,
StoreDispatchQueues, StoreDispatchToSTQ, StoreDispatchSTQPath,
DecodeRenameROBPath, STQEntryBank, TULinkRecoveryCleanupPath,
TULinkFlushSourceSelector, DispatchROBAllocator, reduced ROB
bookkeeping, trace-schema self-test, Chisel QEMU dry-run, and top xcheck
gates. SPERename::Rename snapshots tSeq/uSeq before T/U destination
rename, SPERename::InsertToStoreIEX clones stores after that snapshot, and
MemReqBus carries the sequence sidecars through LSU/STQ cleanup. Preserve
those row-owned sidecars through every split/queue/bridge owner: add them to
StoreSplitIssuePayload, copy them to valid STA/STD/ST_ALL payloads,
preserve them in StoreDispatchQueues, and copy them into
STQStoreRequest. Invalid payloads should expose disabled sidecars, and a
false tuDstValid must force DestinationKind.None. R62 composes
TULinkRename with scalar rename through ScalarTURenameBridge, so reduced
DecodeRenameROBPath must drive live StoreSplitPayload and
DispatchROBAllocator sidecars from that owner; do not reintroduce disabled
producer defaults or discard sidecars in lower owners.
- Phase 5/R62 scalar/TU rename composition work must run
sbt --client --error 'Test / compile' plus affected
ScalarTURenameBridge, DecodeRenameROBPath, ScalarDecodeRenameBridge,
TULinkRename, TULinkRecoveryCleanupPath, TULinkFlushSourceSelector,
StoreSplitPayload, StoreDispatchSTQPath, StoreDispatchToSTQ,
STQEntryBank, DispatchROBAllocator, reduced ROB bookkeeping,
trace-schema self-test, Chisel QEMU dry-run, top xcheck, and LinxCoreModel
SHA gates. Keep ScalarDecodeRenameBridge scalar-GPR-only: sanitize T/U
operands and destinations before feeding it, reject unsupported non-P/T/U
operands, and overlay accepted T/U source/destination physical tags onto the
RenamedUop after scalar rename. Scalar acceptance must be gated by
TULinkRecoveryCleanupPath.ready, and TULinkRecoveryCleanupPath.renameValid
must fire only from the accepted scalar row so GPR and T/U state mutate
atomically. Drive StoreSplitPayload.tSeq/uSeq/tuDst* and
DispatchROBAllocator.allocTSeq/allocUSeq/allocTUDst* from the wrapper's
pre-allocation SPERename::Rename snapshots and accepted T/U destination
sidecar. Keep relation-cmap release/deallocation, old T/U physical tag
release accounting, ready-table mutation, and multi-PE/thread banking in
later owner packets.
- Phase 5/R63 relation-cmap retire-source work must run
sbt --client --error 'Test / compile' plus affected InterfaceBundles,
TULinkRelationCmap, ROBEntryBank, DispatchROBAllocator,
DecodeRenameROBPath, reduced ROB bookkeeping, trace-schema self-test, QEMU
dry-run, and LinxCoreModel SHA gates. Preserve the model SPEROB split:
ROB deallocation publishes width-wide row-owned retire sources, while
TULinkRelationCmap serializes those sources into mark-before-release
commands for TULinkRename.retire*. Do not collapse the ROB deallocation
vector into a single command before a serializer consumes it; otherwise a
commitWidth > 1 dealloc cycle can drop T/U release work. Retire sources
must preserve native bid/gid/rid, isLast, stid, row-owned tSeq/uSeq,
and T/U destination ownership as sidecars rather than reconstructing them
from commit-trace fields. The relation-cmap command order is T pre-release
before U pre-release, current destination mark before post-release, and
pressure release after the fifth same-kind relation, matching
SPEROB::CheckRelativeReg and SPEROB::ReleaseFunc. Ready-table mutation,
old T/U physical tag release accounting, block/group commit cleanup event
wiring, and multi-PE/thread banking remain later owner packets.
- Phase 5/R64 live relation-cmap retire wiring must run
sbt --client --error 'Test / compile' plus affected
TULinkRetireCommandPath, TULinkRelationCmap, ScalarTURenameBridge,
DecodeRenameROBPath, ROBEntryBank, DispatchROBAllocator,
TULinkRename, reduced ROB bookkeeping, trace-schema self-test, and Chisel
QEMU dry-run gates. Keep the ROB deallocation source serializer and
relation-cmap command acceptance as separate handshakes: sourceWindowReady
is full-window FIFO credit for ROB deallocation, while relation-cmap
commandReady must come from actual TULinkRename.retireAccepted, not a
predicted readiness condition. This preserves flush/commit priority inside
TULinkRename and prevents the relation-cmap from dropping a pending
mark/release command when maintenance wins the cycle. Preserve valid
no-destination block-last retire sources; they can still drain older T/U
relations even though they do not emit a current destination mark.
- Phase 5/R65 relation-cmap cleanup pruning work must run
sbt --client --error 'Test / compile' plus affected
TULinkRelationCmap, TULinkRetireCommandPath, DecodeRenameROBPath,
TULinkRecoveryCleanupPath, TULinkRename, ROBEntryBank,
DispatchROBAllocator, reduced ROB bookkeeping, trace-schema self-test,
Chisel QEMU dry-run, diff check, and LinxCoreModel SHA gates. Preserve the
model cleanup split exactly: CleanCMAP(bid) removes all matching
relation entries while preserving remaining order, CleanGroupCMAP(bid, gid) removes all exact (bid,gid) matches while preserving remaining
order, and FlushRelativeReg prunes only the newest suffix of matching
entries. For relation-cmap flush, baseOnBid is inclusive
flush.bid <= entry.bid; non-base is strict BID-only
flush.bid < entry.bid and must not add RID comparison. Apply the same
cleanup predicates to queued ROB dealloc retire sources before they can
enter relation-cmap, so a recovery flush cannot reintroduce pruned relation
work. Keep ready-table side effects and live block/group commit clean event
wiring in separate owner packets.
- Phase 5/R66 ROB block-last deallocation boundary work must run
sbt --client --error 'Test / compile' plus affected ROBEntryBank,
DispatchROBAllocator, DecodeRenameROBPath, TULinkRetireCommandPath,
reduced ROB bookkeeping, trace-schema self-test, Chisel QEMU dry-run, diff
check, and LinxCoreModel SHA gates. Preserve the model SPEROB::dealloc
ordering: call relation release for each retired row, stop the deallocation
window after the first block-last row, and do not expose deallocation sources
from the next block in the same cycle. The block-last deallocation candidate
is only a future CleanCMAP scheduling source; do not fire cleanBlock*
from ROB commit or raw deallocation acceptance because serialized
TULinkRelationCmap mark/release commands for the block-last source must be
accepted first.
- Phase 5/R67 scalar
CleanCMAP scheduling work must run
sbt --client --error 'Test / compile' plus affected
TULinkRetireCommandPath, DecodeRenameROBPath, TULinkRelationCmap,
TULinkRename, ROBEntryBank, DispatchROBAllocator, reduced ROB
bookkeeping, trace-schema self-test, Chisel QEMU dry-run, diff check, and
LinxCoreModel SHA gates. Preserve the model order by latching the BID of the
accepted block-last retire source, blocking later ROB deallocation-source
admission while scalar block clean is pending, allowing existing
relation-cmap mark/release commands to keep draining, and pulsing exact-BID
CleanCMAP only after pendingMark and post-release state clear. Do not
trigger scalar block clean directly from deallocBlockLast*,
sourceDequeued, or ROB commit, and do not include the auto-clean pending
latch in the retire-command commandReady block condition; that would
deadlock the mark/release stream it is waiting for.
- Phase 5/R68 scalar local block-commit event work must run
sbt --client --error 'Test / compile' plus affected
TULinkRetireCommandPath, DecodeRenameROBPath, TULinkRelationCmap,
TULinkRename, ScalarTURenameBridge, ROBEntryBank,
DispatchROBAllocator, reduced ROB bookkeeping, trace-schema self-test,
Chisel QEMU dry-run, diff check, and LinxCoreModel SHA gates. Preserve the
model order ReleaseRelative commands, scalar CleanCMAP, then
ReportLocalRegBlockCommit: the post-clean local block-commit event is a
separate ready/valid boundary for the future SGPR local-register owner, not
a T/U rename commitValid pulse and not an SGPR mutation inside the
relation-cmap owner. While the local commit event is pending, block later ROB
deallocation-source admission until the event is accepted or recovery
prunes it, but do not feed that pending state into retire-command
commandReady.
- Phase 5/R69 scalar local block-commit consumer work must run
sbt --client --error 'Test / compile' plus affected
TULinkRecoveryCleanupPath, ScalarTURenameBridge,
DecodeRenameROBPath, TULinkRetireCommandPath, TULinkRename,
TULinkRelationCmap, ROBEntryBank, DispatchROBAllocator, reduced ROB
bookkeeping, trace-schema self-test, Chisel QEMU dry-run, diff check, and
LinxCoreModel SHA gates. Consume the post-clean
ReportLocalRegBlockCommit event in the live local-register owner:
TULinkRetireCommandPath keeps the event pending, ScalarTURenameBridge
forwards the handshake, and TULinkRecoveryCleanupPath arbitrates it behind
external commit and recovery-flush maintenance before pulsing
TULinkRename.commit* for the reduced T/U bank. Do not route this event
through the relation-cmap scheduler, scalar GPR commit path, or generic
top-level glue. Preserve the reduced scope until a later packet implements
both-SGPR-hand and multi-PE fanout.
- Phase 5/R70 selected-STID local block-commit work must run
sbt --client --error 'Test / compile' plus affected
TULinkRetireCommandPath, TULinkRecoveryCleanupPath,
ScalarTURenameBridge, DecodeRenameROBPath, TULinkRename,
TULinkRelationCmap, ROBEntryBank, DispatchROBAllocator, reduced ROB
bookkeeping, trace-schema self-test, Chisel QEMU dry-run, diff check, and
LinxCoreModel SHA gates. Preserve the model
ReportLocalRegBlockCommit(bid, stid) contract: the post-clean event must
carry the selected STID from the block-last source, and a reduced
local-register owner must accept only its configured local STID. Do not
silently drop or consume a non-local STID event in the reduced bank; keep
ready low and expose a diagnostic until a later fanout owner explicitly
selects or instantiates the matching STID banks across both SGPR hands and
scalar PEs.
- Phase 5/R71 selected-STID local block-commit fanout work must run
sbt --client --error 'Test / compile' plus affected
TULinkLocalBlockCommitFanout, DecodeRenameROBPath,
TULinkRecoveryCleanupPath, ScalarTURenameBridge,
TULinkRetireCommandPath, TULinkRename, TULinkRelationCmap,
ROBEntryBank, DispatchROBAllocator, reduced ROB bookkeeping,
trace-schema self-test, Chisel QEMU dry-run, diff check, and LinxCoreModel
SHA gates. Preserve the model all-selected-PE fanout contract:
ReportSGPRBlockCommit(bid, stid) selects one STID, then updates both SGPR
hands for every scalar PE. A Chisel fanout owner must pulse downstream bank
valid only when every selected PE bank is ready; do not let a ready subset of
banks consume the post-clean block-commit event before the others.
- Phase 5/R72 explicit SGPR local-bank-array work must run
sbt --client --error 'Test / compile' plus affected
TULinkLocalBankArray, ScalarTURenameBridge, DecodeRenameROBPath,
TULinkLocalBlockCommitFanout, TULinkRecoveryCleanupPath,
TULinkRetireCommandPath, TULinkRename, TULinkRelationCmap,
ROBEntryBank, DispatchROBAllocator, reduced ROB bookkeeping,
trace-schema self-test, Chisel QEMU dry-run, diff check, and LinxCoreModel
SHA gates. Preserve the model SGPR bank hierarchy:
sgprRenameUnit[pe][stid][hand] is the owner shape, with T and U as the two
hands inside each PE/STID bank group. Keep selected-STID block-commit fanout
inside the explicit bank-array owner, not in backend glue. Later dynamic
PE/STID routing must target that same bank-array boundary for rename,
retire, recovery cleanup, and local block commit.
- Phase 5/R73 active SGPR bank selector plumbing must run
sbt --client --error 'Test / compile' plus affected
ScalarTURenameBridge, DecodeRenameROBPath, TULinkLocalBankArray,
TULinkRecoveryCleanupPath, TULinkRetireCommandPath, TULinkRename,
TULinkRelationCmap, ROBEntryBank, DispatchROBAllocator, reduced ROB
bookkeeping, trace-schema self-test, Chisel QEMU dry-run, diff check, and
LinxCoreModel SHA gates. Preserve the model SPERename::Rename lookup:
active SGPR bank selection is by row-owned PE/STID at the
ScalarTURenameBridge/TULinkLocalBankArray boundary. In the reduced
backend, derive active STID from the queued decoded row threadId and keep
PE at PE0 until decode carries a PE owner. Keep the active selector scoped
to rename and reduced external maintenance; retired-row mark/release routing
must use the command sidecar path described by R74, not the current
rename-head selector.
- Phase 5/R74 retired-row SGPR retire-bank sidecar work must run
sbt --client --error 'Test / compile' plus affected InterfaceBundles,
TULinkRelationCmap, TULinkRetireCommandPath,
TULinkLocalBankArray, ScalarTURenameBridge, ROBEntryBank,
DispatchROBAllocator, DecodeRenameROBPath,
TULinkRecoveryCleanupPath, TULinkRename, reduced ROB bookkeeping,
trace-schema self-test, Chisel QEMU dry-run, diff check, and LinxCoreModel
SHA gates. Preserve the model SPERename::RepLocalRetired(type, peid, ..., tid) and SPEROB::ReleaseFunc bank arguments: ROB deallocation sources
must carry row-owned peId/stid, relation-cmap entries must retain those
sidecars for later releases, and TULinkRetireCommand must route
mark/release commands by command peId/stid. Do not derive local retire
target banks from ScalarTURenameBridge.activePeId/activeStid; that selector
belongs to the current rename head. Dynamic non-zero PE production remains a
later packet, but the sidecar must be stored, serialized, and diagnosed now.
- Phase 5/R75 decoded/renamed scalar PE owner sidecar work must run
sbt --client --error 'Test / compile' plus affected InterfaceBundles,
F4DecodeWindow, FrontendInstructionBuffer, FrontendDecodeIngress,
FrontendDecodeStage, DecodeLoadStoreIdAssign, DecodeRenameQueue,
ScalarDecodeRenameBridge, ScalarTURenameBridge, StoreSplitPayload,
DecodeRenameROBPath, TULinkLocalBankArray, DispatchROBAllocator,
ROBEntryBank, reduced ROB bookkeeping, top xcheck, trace-schema
self-test, Chisel QEMU dry-run, build, Verilator lint, diff check, and
LinxCoreModel SHA gates. Preserve the model DCTop::Work and
SPERename::Rename ownership chain: frontend packets, decoded uops, renamed
uops, decode/rename queue rows, memory-ID outputs, and store-split payloads
must carry row-owned peId/threadId; reduced DecodeRenameROBPath must
drive ScalarTURenameBridge.activePeId and
DispatchROBAllocator.allocPeId from the queued row peId, while active
STID remains the queued row threadId. Do not reintroduce PE0 constants at
decode, rename, ROB allocation, or store payload boundaries. Nonzero PE
packet production and multi-PE top/bank instantiation remain later owners;
packets that do not set peId still reduce to PE0 through normal zero
defaults.
- Phase 5/R76 enqueue-time ROB reservation is the implemented contract, not an
open design choice. Preserve the model
BCtrlUnit::Work -> DCTop::Work ->
SPEROB::allocROB -> dec_ren_q order: BROB and PE ROB identities are
reserved before the row enters dec_ren_q, not at rename acceptance. In the
C++ model, the ROB row stores the shared SimInst pointer, so later
SPERename mutations such as tSeq/uSeq remain visible through that
pointer. Chisel ROB rows store values, so DecodeRenameROBPath reserves the
row before enqueue and ROBEntryBank.renameUpdate*, forwarded through
DispatchROBAllocator, patches the accepted rename row afterward. Do not
reintroduce queue-head ROB allocation, permanent zero T/U sidecars, or any
allocator-valid feedback loop that lets allocator readiness depend on its own
accepted output. Focused gates include DecodeRenameROBPath,
DispatchROBAllocator, ROBEntryBank, DecodeRenameQueue,
ScalarTURenameBridge, reduced ROB bookkeeping, top xcheck when top IO
changes, trace-schema self-test if commit rows change, Chisel QEMU dry-run,
build, Verilator lint, diff check, and LinxCoreModel SHA gates.
- Phase 5/R77 gate-broadening work starts from the R76 implementation and must
run the full wrapper ladder before wider frontend/rename agents depend on the
new allocation timing: affected R76 unit specs, reduced ROB bookkeeping,
reduced ROB Verilator xcheck, top xcheck, trace-schema self-test, Chisel QEMU
dry-run,
build_chisel.sh, and Verilator lint. R77 may repair wrapper or
trace payload issues found by those gates, but it must not redesign the
reservation/update split without first recording a concrete first-divergence
failure.
- Phase 5/R78 trace replay work adds the bridge between synthetic reduced
smokes and future live QEMU/CoreMark comparison. Run
run_chisel_trace_replay_xcheck.sh after changes to top-level commit export,
trace_schema_adapter.py, or cross-check harness code. The gate must
normalize a bounded external or fixture commit JSONL, replay it through
LinxCoreTop under Verilator, and require zero mismatches against the
QEMU-shaped reference stream. Treat this as replay infrastructure only; it is
not evidence that frontend/decode/execute/LSU generated rows from an ELF.
- Phase 5/R90 QEMU trace replay work adds the bridge from archived or freshly
collected QEMU commit JSONL into the Chisel replay harness. Run
run_chisel_qemu_trace_replay_xcheck.sh --dry-run, then a bounded
--qemu-trace <trace.jsonl> or --elf <direct-boot.elf> replay. Use
--max-commits for architectural compare depth and --replay-rows only as
the raw search/replay cap before metadata filtering. The bridge must report
qemu-replay-raw-rows, qemu-replay-arch-rows, and a passing
crosscheck_manifest.json. It is not full-DUT QEMU equivalence until the
Chisel top emits live commit rows from real fetch/issue/execute/LSU/recovery.
- Phase 5/R91 live-ELF replay prefix work hardens the same bridge for
long-running benchmark ELFs. The FIFO reader must terminate when QEMU exits
early, and direct-boot benchmark images at high physical addresses must pass
explicit QEMU memory. The current CoreMark prefix evidence uses
tests/benchmarks/build/coremark_real.elf with -m 1280M, captures 128 raw
QEMU rows, slices 5 replay rows containing 4 architectural commits, and
requires a passing manifest with zero mismatches.
- Phase 5/R92 shared commit JSONL writer work factors generated-RTL harness
trace emission through
tools/chisel/commit_trace_jsonl.h. Run reduced ROB,
top, trace replay, frontend trace, frontend fetch trace, frontend ALU, and
frontend RF/ALU generated-RTL xchecks after changing this helper or a
harness conversion.
The writer must keep the QEMU architectural field spelling aligned with
QEMU target/linx/helper.c / trace-manager output and keep DUT sidebands
flat for trace_schema_adapter.py; it does not replace the adapter or the
neutral comparator.
- Phase 5/R79 frontend-window trace-top work adds the first emitted Chisel top
boundary that drives a raw
FrontendDecodePacket window through
F4DecodeWindow and DecodeRenameROBPath before monitored commit export.
Run run_chisel_tests.sh --only LinxCoreFrontendTraceTop and
run_chisel_frontend_trace_top_lint.sh after changes to that
frontend-window-to-commit boundary. The wrapper may use an external
completion surrogate until execute owners exist; it is not full
QEMU/CoreMark evidence until a Verilator driver dumps DUT commit JSONL from
live frontend/decode/execute/LSU-owned rows.
- Phase 5/R80 frontend-window trace-top xcheck work adds the first generated
RTL comparison gate for
LinxCoreFrontendTraceTop. Run
run_chisel_frontend_trace_top_xcheck.sh after changes to the frontend
trace-top driver, temporary completion surrogate, trace dump, or commit
export. The gate must drive raw scalar frontend packets through
F4DecodeWindow and DecodeRenameROBPath, use the explicit completion
surrogate to retire allocated ROB rows, dump DUT JSONL, and require zero
mismatches against a QEMU-shaped reference stream. Treat this as frontend
packet to commit-row infrastructure only; it is still not CoreMark/QEMU
architectural evidence until fetch, issue, execute, LSU, and recovery owners
generate the retired rows and completion payloads.
- Phase 5/R94 live frontend fetch trace-top work adds the first generated RTL
comparison gate where a Chisel source, not the testbench, creates
FrontendDecodePacket rows from PC request/response handshakes. Run
run_chisel_tests.sh --only FrontendFetchPacketSource,
run_chisel_tests.sh --only LinxCoreFrontendFetchTraceTop, and
run_chisel_frontend_fetch_trace_top_xcheck.sh after changes to the live
frontend fetch source top, bounded memory-window fixture, source-to-F4
handshake, temporary completion surrogate, or commit export. The fixture may
expose one valid F4 slot per response while the reduced backend remains
one-selected-row-per-packet. Treat this as live source-to-F4-to-ROB
infrastructure only; it is not full QEMU/CoreMark evidence until ELF memory,
dense packets, real execute/LSU completion, and recovery are live.
- Phase 5/R95 live frontend fetch RF-backed ALU trace-top work composes the
live fetch source with the reduced RF-backed issue and ALU completion path.
Run
run_chisel_tests.sh --only FrontendFetchPacketSource,
run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop, and
run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh after changes to the
live fetch source to RF/issue/ALU top, bounded memory-window fixture,
source-to-F4 handshake, source PC advance, issue enqueue, RF source
readiness, ALU completion, RF writeback, or commit export. Keep
run_chisel_frontend_fetch_trace_top_xcheck.sh and
run_chisel_frontend_rf_alu_trace_top_xcheck.sh as regressions for the two
predecessor surfaces. Treat this as live-source RF/ALU infrastructure only;
it is not full QEMU/CoreMark evidence until ELF memory, dense packets, full
issue arbitration, LSU, trap/recovery, and redirect restart are live.
- Phase 5/R97 sparse ELF fetch-memory work extends the same live fetch
RF/ALU gate with program-image input support. Run
python3 tools/chisel/frontend_fetch_elf_memory.py --self-test after
changes to ELF extraction, sparse fetch-memory format, or FETCH_ELF
wrapper routing. Use
FETCH_ELF=<elf> bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh
to exercise ELF64 little-endian PT_LOAD extraction into
generated/chisel-frontend-fetch-rf-alu-trace-top-xcheck/elf.fetch.mem.
This proves sparse/high-address program bytes can feed the live source
response path, but it still uses the reduced top's expected row lengths and
fixed scalar reference rows. Do not claim QEMU/CoreMark equivalence until a
later packet binds expected rows to a bounded QEMU/ELF prefix and removes the
single-instruction response constraint.
- Phase 5/R98 external expected-row source work splits live fetch RF/ALU
expected rows from the C++ harness. Run
python3 tools/chisel/frontend_fetch_rf_alu_fixture_rows.py --self-test
after changing the default row fixture. The wrapper emits
generated/chisel-frontend-fetch-rf-alu-trace-top-xcheck/fixture.expected.jsonl
unless FETCH_EXPECTED_ROWS=<rows.jsonl> points at another QEMU-shaped row
stream, then passes --expected-rows to the Verilator harness and sizes the
comparator window from the expected row count. This is a row-source contract
for reduced scalar live-fetch rows, not full QEMU/CoreMark equivalence:
broader QEMU/ELF prefixes, dense packets, LSU, trap/recovery, and live
full-DUT commit generation remain later owners.
- Phase 5/R99 strict QEMU trace expected-row extraction work feeds that same
row-source boundary from an existing QEMU commit JSONL. Run
python3 tools/chisel/frontend_fetch_rf_alu_qemu_rows.py --self-test after
changes to the extractor, and use
FETCH_QEMU_TRACE=<qemu.jsonl> bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh
to normalize and validate a strict sequential reduced-scalar prefix into
generated/chisel-frontend-fetch-rf-alu-trace-top-xcheck/qemu.expected.jsonl.
FETCH_QEMU_MAX_ROWS=<n> caps the extracted row count, while 0 means all
normalized input rows. The extractor must reject unsupported opcodes, memory
or trap side effects, non-scalar GPR aliases, non-sequential next_pc, and
writeback/result mismatches before the Verilator harness runs. This remains
reduced ADD/ADDI/ADDTPC/C.MOVI/C.MOVR evidence only; dense packets, LSU,
trap/recovery, and live full-DUT commit generation remain later owners.
- Phase 5/R100 live QEMU ELF capture work binds the R99 row-source path to a
direct-boot ELF. Build the legal-entry fixture with
bash tools/chisel/build_frontend_fetch_rf_alu_qemu_fixture_elf.sh --out-dir generated/r100-live-qemu-fixture,
then run
bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --elf generated/r100-live-qemu-fixture/frontend_fetch_rf_alu_qemu_fixture.elf --expected-rows 3 --capture-rows 3 --pc-lo 0x10002 --pc-hi 0x1000b --max-seconds 5.
The wrapper captures bounded QEMU rows through a FIFO, validates them with
frontend_fetch_rf_alu_qemu_rows.py, extracts matching bytes through
FETCH_ELF, and runs the live fetch RF/ALU comparator. Use --pc-lo /
--pc-hi to skip legal entry BSTART until block-header execution is live
in the DUT. A signal-15 QEMU termination after bounded capture is expected
only when the manifest reports status: "pass". The Verilator harness must
derive initial RF preloads from first expected source reads; do not re-add
synthetic-only hardcoded source values.
- Phase 5/R101 reduced block-marker work lets that same legal-entry ELF run
without scalar PC filters. Build the fixture with
bash tools/chisel/build_frontend_fetch_rf_alu_qemu_fixture_elf.sh --out-dir generated/r101-live-qemu-fixture,
then run
bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --elf generated/r101-live-qemu-fixture/frontend_fetch_rf_alu_qemu_fixture.elf --expected-rows 0 --capture-rows 5 --allow-block-markers --max-seconds 5.
--allow-block-markers preserves legal BSTART/BSTOP rows as DUT-only
skip entries: the generated-RTL harness must fetch and decode them, assert
marker diagnostics, and require no ROB allocation or issue enqueue. The
comparator still receives only non-skip scalar commit rows. Treat this as
reduced marker-consume evidence, not dense packet support and not full
BSTART/BSTOP scalar_done/BROB retirement semantics.
- Phase 5/R102 reduced dense D1-slot work lets the same live fetch RF/ALU gate
feed natural 8-byte F4/IB windows instead of one instruction per response. The
reduced bridge must preserve every valid D1 slot from the window in order,
keep each slot's original slot index, and drain one slot per cycle into the
existing serialized decode/ROB path. Build the fixture with
bash tools/chisel/build_frontend_fetch_rf_alu_qemu_fixture_elf.sh --out-dir generated/r102-live-qemu-fixture,
then run
bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r102-dense-qemu-elf-xcheck --elf generated/r102-live-qemu-fixture/frontend_fetch_rf_alu_qemu_fixture.elf --expected-rows 0 --capture-rows 5 --allow-block-markers --max-seconds 5.
Marker-slot checks are marker-owned: a marker drain must not select a scalar
row, push dec/ren, or allocate ROB for that marker, but it may overlap an
older scalar row's issue enqueue in the same cycle. This is still not full
width-wide ROB allocation or BSTART/BSTOP scalar_done/BROB retirement.
- Phase 5/R106 CoreMark ADDTPC work extends the reduced live fetch RF/ALU
envelope with the model PC-relative constant operation.
ADDTPC must compute
(pc & ~0xfff) + imm, where frontend operand decode has already
sign-extended IMM20 and shifted it left by 12. Run
bash tools/chisel/run_chisel_tests.sh --only ReducedScalarAluExecute,
python3 tools/chisel/frontend_fetch_rf_alu_qemu_rows.py --self-test, and
bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r106-coremark-addtpc-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 4 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf
after changing reduced PC-relative execute or QEMU extraction. The R106
evidence compares three scalar rows (C.MOVR, ADDTPC, ADDI) with zero
mismatches and preserves C.BSTART as a skip marker; the next observed
CoreMark blocker is the 6-byte HL call marker at pc=0x40005500.
- Phase 5/R107 CoreMark HL-call work extends the reduced live fetch RF/ALU
envelope through the first direct-call header. QEMU can emit
HL.BSTART.STD CALL as a duplicate zero-advance marker row followed by the
advancing marker row; the extractor should drop only the zero-advance marker
artifact when it has no trap, memory, or writeback side effects. Compact
C.SETRET aliases the C.MOVI low-opcode form when the destination is
ra/x10, forces destination x10, uses uimm5 << 1, and computes
pc + imm; do not route it through ADDTPC or generic C.MOVI
semantics. Target-bearing BSTART forms must carry boundaryTarget = pc + imm, F4DecodeWindow must stop exposing later slots after a valid
C.BSTOP, and the reduced live-fetch top may apply a frontend-only restart
to the active BSTART target when C.BSTOP closes the marker-owned block.
Run the focused gates
bash tools/chisel/run_chisel_tests.sh --only F4DecodeWindow,
bash tools/chisel/run_chisel_tests.sh --only FrontendDecodeStage,
bash tools/chisel/run_chisel_tests.sh --only DecodeRenameROBPath,
bash tools/chisel/run_chisel_tests.sh --only ReducedScalarAluExecute,
bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop,
bash tools/chisel/run_chisel_tests.sh --only FrontendDecodeIngress,
python3 tools/chisel/frontend_fetch_rf_alu_qemu_rows.py --self-test, and
bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r107-coremark-hl-call-setret-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 8 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf
after changing compact SETRET decode, target-bearing BSTART decode,
marker-stop redirect wiring, or live-QEMU row extraction. The R107 evidence
compares four scalar rows with zero mismatches and advances the next
CoreMark blocker to the row after pc=0x4000550e.
- Phase 5/R108 CoreMark FENTRY work extends the reduced live fetch RF/ALU
envelope through the first single-save macro prologue row. Treat this as a
narrow reduced FENTRY shape only: map the saved GPR field to an internal RF
read, map old SP (
x1) to another internal RF read, mark SP (x1) as the
reduced destination, write SP - imm, and emit the one QEMU-shaped 8-byte
store sideband while suppressing those internal source fields in the commit
row. The expected-row reducer must preserve FENTRY memory fields and should
reject multi-register FENTRY until stack-template/LSU semantics are owned.
Run
python3 tools/chisel/frontend_fetch_rf_alu_qemu_rows.py --self-test,
bash tools/chisel/run_chisel_tests.sh --only FrontendDecodeStage,
bash tools/chisel/run_chisel_tests.sh --only ReducedScalarAluExecute,
bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop,
and
bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r108-coremark-fentry-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 11 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf
after changing reduced FENTRY decode, execute, memory sideband comparison, or
QEMU extraction. The next observed 12-row CoreMark blocker is an ADDI
writing architectural tag 30, outside the reduced scalar GPR namespace.
- Phase 5/R109 CoreMark U-destination ADDI work extends the reduced live fetch
RF/ALU envelope through that local-register destination row. Preserve the
model alias split: destination tag
30 is DestinationKind.U, not a scalar
GPR. ScalarTURenameBridge owns the T/U destination overlay; reduced issue
and execute owners must gate scalar RF clear/write side effects to
DestinationKind.Gpr while still emitting QEMU-shaped architectural
dst_reg=30 / wb_rd=30 commit fields. The expected-row reducer may accept
this U-destination only for the current reduced ADDI row and must continue
rejecting unsupported T/U source reads. Run
python3 tools/chisel/frontend_fetch_rf_alu_qemu_rows.py --self-test,
bash tools/chisel/run_chisel_tests.sh --only ReducedScalarIssueQueue,
bash tools/chisel/run_chisel_tests.sh --only ReducedScalarAluExecute,
bash tools/chisel/run_chisel_tests.sh --only ScalarTURenameBridge,
bash tools/chisel/run_chisel_tests.sh --only DecodeRenameROBPath,
bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendRfAluTraceTop,
bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop,
and
bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r109-coremark-u-dst-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 12 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf
after changing reduced T/U destination handling, RF writeback gating, or
live-QEMU row extraction. The R109 evidence compares seven scalar/macro rows
with zero mismatches. A 13-row probe advances the next blocker to OP_HL_LUI
at pc=0x4000551a, insn=0x1f97000e, len=6.
- Phase 5/R110 CoreMark HL.LUI work extends the reduced live fetch RF/ALU
envelope through that T-destination immediate row. Preserve the same local
register split as R109: destination tag
31 is DestinationKind.T, not a
scalar GPR. OP_HL_LUI materializes the sign-extended 48-bit-format IMM32
payload directly into the destination; frontend operand decode packs
Cat(pfx16[15:4], main32[31:12]) before execute receives imm. The
expected-row reducer may accept this T-destination only for the current
reduced HL.LUI row and must continue rejecting unsupported T/U source
reads. Run
python3 tools/chisel/frontend_fetch_rf_alu_qemu_rows.py --self-test,
bash tools/chisel/run_chisel_tests.sh --only FrontendDecodeStage,
bash tools/chisel/run_chisel_tests.sh --only ReducedScalarAluExecute,
bash tools/chisel/run_chisel_tests.sh --only ScalarTURenameBridge,
bash tools/chisel/run_chisel_tests.sh --only DecodeRenameROBPath,
bash tools/chisel/run_chisel_tests.sh --only ReducedScalarIssueQueue,
bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop,
and
