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foundry-rtl-workflow

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UpdatedJuly 14, 2026 at 01:39

Use for foundry RTL tasks involving ChipCraftX RTL generation, model-route evidence, GitHub implementation issues, and handoff to EDA validation.

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rajshah4

rajshah4/semi-demo

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Electronics Engineers, Except ComputerArchitecture and Engineering Occupations·SOC 17-2072

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SKILL.md

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name	foundry-rtl-workflow
description	Use for foundry RTL tasks involving ChipCraftX RTL generation, model-route evidence, GitHub implementation issues, and handoff to EDA validation.

Foundry RTL Workflow

Core Rule

OpenHands orchestrates the workflow. Specialist models generate or summarize. EDA tools validate.

Model Roles

Sonnet-style orchestrator: planning, edits, final judgment
SambaNova Llama 3.3 70B: fast log triage and repeated small loops
ChipCraftX RTLGen 7B: Verilog/SystemVerilog generation and repair

Required Evidence

Every completed run should report:

event or issue that triggered the run
model route used
files changed
validation commands
pass/fail status
unresolved risks

Skill-Owned Scripts

scripts/chipcraftx_generate_rtl.py: calls the configured ChipCraftX Hugging Face provider route and writes generated RTL plus metadata under artifacts/chipcraftx/.

Run it from the repository root:

python3 skills/foundry-rtl-workflow/scripts/chipcraftx_generate_rtl.py \
  --summary "<issue title and concise RTL requirements>" \
  --max-new-tokens 700 \
  --retries 5

Use the generated RTL as a first draft only. The orchestrator still owns code review, integration into examples/sync_fifo/sync_fifo.sv, validation, PR evidence, and human-review framing.

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name	foundry-rtl-workflow
description	Use for foundry RTL tasks involving ChipCraftX RTL generation, model-route evidence, GitHub implementation issues, and handoff to EDA validation.

Foundry RTL Workflow

Core Rule

OpenHands orchestrates the workflow. Specialist models generate or summarize. EDA tools validate.

Model Roles

Sonnet-style orchestrator: planning, edits, final judgment
SambaNova Llama 3.3 70B: fast log triage and repeated small loops
ChipCraftX RTLGen 7B: Verilog/SystemVerilog generation and repair

Required Evidence

Every completed run should report:

event or issue that triggered the run
model route used
files changed
validation commands
pass/fail status
unresolved risks

Skill-Owned Scripts

scripts/chipcraftx_generate_rtl.py: calls the configured ChipCraftX Hugging Face provider route and writes generated RTL plus metadata under artifacts/chipcraftx/.

Run it from the repository root:

python3 skills/foundry-rtl-workflow/scripts/chipcraftx_generate_rtl.py \
  --summary "<issue title and concise RTL requirements>" \
  --max-new-tokens 700 \
  --retries 5

Use the generated RTL as a first draft only. The orchestrator still owns code review, integration into examples/sync_fifo/sync_fifo.sv, validation, PR evidence, and human-review framing.