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formal

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UpdatedJuly 24, 2026 at 01:23

Formal verification flow - SymbiYosys via sv2v flatten, in-RTL ifdef FORMAL properties, mutation-checking every new assertion, harness vacuity traps. Use when writing properties, regenerating proofs, or after changing any module with a formal dir.

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sean-galloway

sean-galloway/RTLDesignSherpa

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SKILL.md

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name	formal
description	Formal verification flow - SymbiYosys via sv2v flatten, in-RTL ifdef FORMAL properties, mutation-checking every new assertion, harness vacuity traps. Use when writing properties, regenerating proofs, or after changing any module with a formal dir.

formal

READ FIRST: vault/handbook/dv/formal.md (the handbook is the repo's memory; this skill is the signpost). sv2v deletes assertions without --exclude=Assert; mutation-check every property; watch the vacuity traps; BMC-25 is not induction.

The handbook root is vault/handbook/INDEX.md - design/, dv/, fpga/ areas, atomic notes, wikilinked. When you learn a durable lesson in this domain, ADD IT TO THE HANDBOOK NOTE, not to this skill.

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