Create and operate canonical SoC project/module scaffolds through registered MCP tools for filelists, lint, compile, simulation, regression, coverage, and synthesis. Use for SoC project setup and any EDA Make-target execution.
Close stale multi-stage SoC delivery evidence for a router-selected merge or signoff packet. Use only when vibe-soc-loop delegates final architecture, doc, RTL, verification, synthesis, integration, or PD closure; do not use for ordinary dev iterations.
Route one-sentence vibe_soc feature, RTL, integration, verification, synthesis, register, CRG, low-power, or PD requests into the smallest safe Loop execution packet. Use for SoC work that needs task classification, MCP selection, pipeline state, or delivery closure.
Generate Synopsys .db technology or stub libraries for early synthesis and link. Use when converting Liberty .lib to .db with lc_shell, or when creating a minimal black-box Liberty/.db from a Verilog top module port list.
Prepare and run local-default OpenROAD-flow-scripts physical-design handoff for silicon-crew SoC projects. Use when Codex needs to generate ORFS config/SDC under pd/openroad, run synth/floorplan/place/cts/route/finish/all stages through the default local ORFS path or explicit container backends, summarize OpenROAD reports/results, or connect vibe_soc-style RTL projects to OpenROAD.
Convert reviewed clock/reset Excel design tables into Draw.io and Excalidraw topology diagrams. Use for CRG source, mux, divider, OCC, ICG, and reset-chain visualization.
Convert a CRG requirement table into clock/reset design tables, PLL recommendations, and an architecture report. Use before clock/reset diagram generation when requirements are supplied as Excel or CSV.
Generate YAML and Verilog register-file artifacts from a structured Excel register workbook. Use when the approved register source is an Excel sheet.