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analog-flow-orchestrate

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UpdatedJuly 17, 2026 at 00:40

Canonical reference doc for the Analog A1-A9 track — spec extraction → topology → netlist → corner sweep → layout → per-block PV (DRC/LVS) → post-layout resim → hardmacro → HIL. Used when an agent wants to walk the A1-A9 plan step-by-step. For unified one-command execution (deterministic runner + AI fall-through + final audit aggregated), prefer the slash command `/vibe-ic-analog` (v1.6.13+) which merges this skill's workflow with `analog_one_shot_runner.py`.

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spec-to-rtl

vibeic/vibe-ic

MANDATORY entry point when `design_one_shot_runner.step_rtl_gen` WAIVES with `fallback_skill='spec-to-rtl'`. This is invoked for every IC class with `rtl_gen=null` in `ic_class_registry.json` (currently: digital_arithmetic_primitive, digital_cmd_driven, bare_fpga, processor_cpu, unknown_protocol_class). The runner has already (1) ingested the prompt into L1-L27, (2) detected the IC class, (3) set the expected RTL path. This skill authors synthesizable RTL into the runner's expected path so the runner's downstream gates (chip_top auto-emit, rtl_hygiene_lint --fix, eda_lint, eda_synth, eco_loop, spec_conformance_check, full_stack_tb_gen) can fire on it. Triggered automatically by the runner's WAIVE message; also fires on phrases like 'AI invokes spec-to-rtl', 'runner WAIVED rtl_gen', 'spec-to-rtl handoff'. THIS IS THE RUNNER'S INTENDED PATH — NOT BYPASS. Bypass means authoring with MCP outside the runner's pipeline (what the 2026-05-28 wrong-shape RTLLM 37/50 did).

2026-07-2616

core-agent-loop

vibeic/vibe-ic

Closed-loop core-agent that fixes plugin issues filed by the field-agent. Invoke as a cron prompt; the loop polls the repo for ANY OPEN non-PR issue (new OR reopened — no label gating, no comment classifier), reproduces and fixes the bug chip-AGNOSTIC-ally, SELF-VERIFIES (reproduce + run the cadence-correct plugin test suite the CI way), then SHIPS by DIRECT PUSH (2026-06-26 owner directive — direct commit + `git push origin main`, no PR ceremony) gated by `gatekeeper_review.py --role core-agent` (MERGE_OK) + Step-2.7 + `gatekeeper_assign_version.py --write` (the pusher assigns the monotonic version pre-push) — posts a 繁體中文 fix comment in the canonical 5-section shape (incl 本機驗證 evidence), then `gh issue close` + adds the `core-closed` label. CLOSED is the terminal state; the field-agent audits closed issues on the real benchmark and reopens any it finds inadequate.

2026-07-2616

flow-change-acceptance

vibeic/vibe-ic

MANDATORY before landing any change to the FLOW itself — a gate, a check, a step, a phase runner, a verdict rule, or anything under programs/ that every design passes through. Flow-level changes are foundational: when they are right every cell benefits, and when they are wrong every cell lies at once and nobody notices. This skill is the acceptance standard for that class of change: bidirectional negative control (a test that cannot fail against the pre-fix code proves nothing), corpus sweep with zero false positives, prove-by-run that a gate declared BLOCKING actually stops the flow, no design/PDK/vendor literals, an explicit BLOCKING-vs-ADVISORY declaration, and degrade-loudly-never-silently. Every criterion here was written from a measured failure in this repo, cited inline. Triggers on: authoring or reviewing a gate/check/step, 'add a gate', 'this check should catch', 'why did the flow not catch', 'land a flow fix', 'flow-level change', '流程層改動', '加一個檢查', '這個 gate 為什麼沒擋住'.

2026-07-2616

catalog-glue-author

vibeic/vibe-ic

When design_one_shot_runner.step_rtl_gen WAIVES rtl_gen and ip_catalog_query has emitted matches, this skill pulls the matched open-source IP RTL into the project's canonical phase2/stage1/rtl/ directory and authors only the integration wrapper / chip-top + OpenLane config glue from L1-L27 spec. Replaces full-from-scratch spec-to-rtl authoring for SoC-class designs where pre-validated open-source IPs exist in the catalog. Triggers automatically when phase2 WAIVES with `fallback_skill=catalog-glue-author`.

2026-07-2616

layer-contract-doctrine

vibeic/vibe-ic

Read BEFORE authoring or revising an L-layer emitter, an L-layer schema field, or a layer gate. Answers the three questions no program can decide for you — WHICH of the 27 layers a given fact belongs in (the layer that CONSUMES it, not any layer that mentions it), WHETHER the thing you are specifying is structural (closed, enumerable, correct-by-construction, therefore a program) or behavioural (no unique correct implementation, therefore synthesis and not expansion), and WHETHER a declarative layer should align to IP-XACT / SystemRDL semantics instead of inventing schema. Produces a Layer Contract Decision record. Pairs with l_doc_consumer_contract.py.

2026-07-2616

sta-review

vibeic/vibe-ic

Read Static Timing Analysis reports, triage setup/hold/recovery/removal violations, and propose fixes (RTL pipelining, sizing, useful skew, buffer insertion). Use when the user says "STA", "timing report", "timing violation", "setup fail", "hold fail", "close timing", "WNS", "TNS".

2026-07-2516

name

analog-flow-orchestrate

description

Analog Flow Orchestrate — 9-STEP ANALOG TRACK

Doctrine (v0.1.50): 把修法寫進工具，而非寫進 prompt. Programs first (runner + 9 A-step check gates); AI is the backstop.

Mandatory Deterministic Preflight

# 1. Drive the deterministic runner first:
python3 plugins/vibe-ic/programs/analog_one_shot_runner.py <project>

# 2. After each A-step, the corresponding check gate runs deterministically:
python3 plugins/vibe-ic/programs/analog_a1_spec_extract_check.py
python3 plugins/vibe-ic/programs/analog_a2_topology_select_check.py
python3 plugins/vibe-ic/programs/analog_a3_netlist_gen_check.py
python3 plugins/vibe-ic/programs/analog_a4_corner_sweep_check.py
python3 plugins/vibe-ic/programs/analog_a5_layout_check.py
python3 plugins/vibe-ic/programs/analog_a6_block_pv_check.py
python3 plugins/vibe-ic/programs/analog_a7_post_layout_resim_check.py
python3 plugins/vibe-ic/programs/analog_a8_hardmacro_gen_check.py
python3 plugins/vibe-ic/programs/analog_a9_hw_verify_check.py

# 3. Ordering gate — A8 must finish before digital Step 15 floorplan
#    (Hard rules #1 + #2), enforced deterministically:
python3 plugins/vibe-ic/programs/analog_a8_before_floorplan_check.py <project>

The skill is the CANONICAL REFERENCE for A1-A9 semantics. **The runner

9 step-check programs are the source of truth for PASS / FAIL.** Refuse to override their verdicts.

Merged into /vibe-ic-analog slash command (v1.6.13+). This skill remains as the canonical reference for the A1-A9 step semantics, the per-step skill mapping, and the gate-predicate definitions. The slash command implements the orchestration workflow described here so the agent does not have to invoke skill + runner separately. Use this skill directly when you want the A1-A9 plan without first running the deterministic runner; otherwise prefer /vibe-ic-analog.

The analog counterpart to flow-orchestrate. Manages the complete analog design pipeline from spec extraction through hardware-verified convergence to hardmacro packaging. Runs in parallel with the digital track (Steps 1-13), converging before digital Step 15 (Floorplan; was Step 14 pre-Wave-91).

Scope

Input: generated_docs/L1_DATASHEET.json + generated_docs/L5_ADI_SPEC.json + PDK
Output: hardmacro/<block>/ deliverables (GDS + LEF + Liberty + behavioral Verilog) per analog block
Decision: PASS iff analog_flow_compliance_check exits 0

The 9 steps

#	Step	Skill	Gate
A1	Analog Spec Extraction	`analog-spec-extract`	`analog/<block>/spec.json` per detected block
A2	Topology + Initial Sizing	`analog-topology-select` + `analog-sizing`	`topology.md` + `sizing.md` per block
A3	Netlist Generation	`analog-netlist-gen`	`analog_netlist_pdk_check` exits 0
A4	Corner Sweep + Optimization	`analog-sizing-loop`	`analog_corner_sweep_check` exits 0
A5	Analog Layout	`analog-layout` + `eda_analog_layout`	`layout.mag` per block
A6	Per-Block Physical Verification (DRC + LVS)	`drc-fix` + `lvs-triage`	`analog_a6_block_pv_check` exits 0
A7	Post-Layout Extraction + Resim	`analog-extraction-resim`	`analog_pre_vs_post_layout_check` exits 0
A8	Hardmacro Generation	`analog-hardmacro-gen`	`analog_hardmacro_check` exits 0
A9	HW Verification + Mixed-Signal	`analog-hw-tuning-loop` + `mixed-signal-cosim`	`analog_hw_spice_correlation_check` + `mixed_signal_cosim_check` exit 0

v1.6.14 Wave 90 — step renumber. Pre-release decimal/sub-step ids were integerised; the analog track is now A1-A9 (A1-A5 unchanged, per-block PV is A6, Resim/Hardmacro/Cosim are A7/A8/A9).

Hard rules

A8 must complete BEFORE digital Step 15 (Floorplan). Digital PnR needs the LEF/Liberty/GDS to place analog blocks. Enforced by programs/analog_a8_before_floorplan_check.py — FAILs when a floorplan DEF exists but any analog block is still missing its A8 hardmacro LEF.
A9 (and only A9) can run in parallel with digital Steps 15+. Hardware verification doesn't block physical design. Corollary enforced by the same analog_a8_before_floorplan_check.py ordering gate (every step ≤ A8 must precede floorplan; A9 is the sole exception).
No step is optional. If hardware is unavailable for A9, write a waiver. Enforced by programs/analog_flow_compliance_check.py (every step is PASS or carries a waiver in analog/waivers.json).
Emit the 9-row plan table BEFORE any step runs. User must see all 9 steps up front. This is an interaction/presentation rule (LLM-driven) — the deliverable-presence half is covered by analog_flow_compliance_check.py.

Orchestration workflow

plan → execute_step_AN → gate_AN → observe → (retry ≤3 or abort) → next step
                                                ↓
                                       final: analog_flow_compliance_check

Detect: Read generated_docs/L5_ADI_SPEC.json or scan RTL for analog modules. Enforced by programs/analog_block_coverage_check.py + programs/analog_content_detected_must_emit_l5_check.py (deterministic JSON-read / module-scan; FAILs if docs document analog content but L5 omits it).
Plan: Emit 9-row table with all blocks × 9 steps (LLM presentation step).
Execute: Walk A1→A9 in order. For each block, run the named skill. The A1→A9 dispatch table + state machine is the deterministic programs/analog_one_shot_runner.py (source of truth, not this prose).
Gate: After each step, run its A-step gate program. Retry decision on failure — what to change before retry, and abort-vs-continue — is the LLM backstop (see "Per-step retry / abort" below).
Report: Write analog/status.json (program-emittable) + analog/flow_summary.md (LLM narrative).
Final gate: programs/analog_flow_compliance_check.py must exit 0, and the ordering gate programs/analog_a8_before_floorplan_check.py must not FAIL.

Per-step retry / abort (LLM backstop — KEEP)

When an A-step gate FAILs, the deterministic runner reports which gate failed; deciding what to change before the retry (resize a device, pick a different topology, relax a corner, loosen a layout constraint) and whether to abort vs continue after ≤3 retries is genuine engineering judgment that cannot be reduced to a fixed program. The same applies to the STOP-and-ask branch under "Inputs to gather" — clarifying ambiguous / missing PDK, block list, HW availability or target specs from a human is interaction, not a check.

Timing integration with digital track

Digital Track            Analog Track
Step 1: spec-to-rtl      A1: spec extraction    ← both start from L1-L27
Step 2: lint              A2: topology + sizing
Step 3: CDC/RDC           A3: netlist gen
Step 4: simulation        A4: corner sweep
Step 5: formal            A5: analog layout
Step 6: FPGA proto        A6: per-block DRC/LVS
Step 7-13: synth+DFT      A7: extraction + resim
                          A8: hardmacro gen
                                ↓ A8 DONE
Step 14: pre-PnR Yosys gate (Wave 91 sentinel)
Step 15: Floorplan  ◄─── hardmacro LEF/GDS placed
Step 16-28: PnR+STA       A9: HW verification (parallel)
Step 29-36: signoff       A9: mixed-signal cosim

Inputs to gather (must be explicit before starting)

PDK (gf180 or sky130)
Which analog blocks to design (from L5 or user specification)
Hardware availability (FPGA board + scope for A9)
Target specs per block (from L1 or user specification)

If any input is missing, STOP and ask.

Output format

`analog/status.json`

{
  "blocks": ["ldo_1v8", "por", "rc_osc"],
  "steps": {
    "ldo_1v8": {
      "A1": {"status": "PASS", "started": "...", "ended": "..."},
      "A2": {"status": "PASS"},
      "A3": {"status": "PASS"},
      "A4": {"status": "PASS", "iterations": 3},
      "A5": {"status": "PASS"},
      "A6": {"status": "PASS", "drc_clean": true, "lvs_match": true},
      "A7": {"status": "PASS", "degradation_pct": 8.2},
      "A8": {"status": "PASS"},
      "A9": {"status": "PASS", "hw_verified": true, "cosim_pass": true}
    }
  },
  "all_pass": true
}

`analog/flow_summary.md` — human-readable summary

Do not

Do not skip A1-A4 (SPICE convergence) and jump to hardware (A9)
Do not generate hardmacros (A8) before post-layout verification (A7)
Do not declare PASS without analog_flow_compliance_check exit 0
Do not block the digital track — A9 is the only step that can run past Step 15

Compliance gate (MANDATORY)

At end of analog flow, run:

python3 plugins/vibe-ic/programs/analog_flow_compliance_check.py \
    <project_dir> --json <project_dir>/reports/analog_compliance.json

Exit 0 → declare PASS. Exit 1 → list failures and recommend next action.

Compliance gate (mandatory)

After producing your output, save it to a file and run:

python3 plugins/vibe-ic/_shared/skill_compliance_check.py \
    --requirements plugins/vibe-ic/skills/analog-flow-orchestrate/compliance.yaml \
    <your_output_file>

Exit 0 = PASS, exit 1 = FAIL with specific missing elements listed.

Your task is not complete until the audit returns PASS.

analog-flow-orchestrate

More from this repository

More from this repository

Analog Flow Orchestrate — 9-STEP ANALOG TRACK

Mandatory Deterministic Preflight

Scope

The 9 steps

Hard rules

Orchestration workflow

Per-step retry / abort (LLM backstop — KEEP)

Timing integration with digital track

Inputs to gather (must be explicit before starting)

Output format

analog/status.json

analog/flow_summary.md — human-readable summary

Do not

Compliance gate (MANDATORY)

Compliance gate (mandatory)

Analog Flow Orchestrate — 9-STEP ANALOG TRACK

Mandatory Deterministic Preflight

Scope

The 9 steps

Hard rules

Orchestration workflow

Per-step retry / abort (LLM backstop — KEEP)

Timing integration with digital track

Inputs to gather (must be explicit before starting)

Output format

analog/status.json

analog/flow_summary.md — human-readable summary

Do not

Compliance gate (MANDATORY)

Compliance gate (mandatory)

`analog/status.json`

`analog/flow_summary.md` — human-readable summary

`analog/status.json`

`analog/flow_summary.md` — human-readable summary