name	minifpga-quartus
description	Develop and debug Intel Quartus projects for the user's MiniFPGA Cyclone IV E board. Use when Codex needs to read FPGA lab PDFs/DOCX, generate Verilog experiments such as LED flow, counters, DDS, or frequency meters, assign MiniFPGA pins, compile with Quartus, program or solidify through USB-Blaster/JTAG/EPCS, or configure/open SignalTap for waveform observation.

MiniFPGA Quartus

Operating Rules

Treat this as a hardware workflow, not just code generation. Read the lab document first, identify the required top-level ports, map every physical I/O intentionally, compile, verify timing, then program.

Use the command-line Quartus flow by default. The verified installation path is D:\Software\intelFPGA\18.1\quartus\bin64; still detect or accept another path if the user provides one.

Never program or solidify a build with negative setup/hold slack unless the user explicitly asks for a temporary unsafe test. Fix timing first, then download.

Do not invent unknown header pins. If the user has not provided external module pins, either ask for the header mapping or use clearly marked temporary pins such as LEDs for digital verification.

Preserve user changes in the worktree. Do not revert unrelated files.

Reference Routing

Read only what the task needs:

Board pins and fixed assignments: references/board-minifpga.md
Quartus compile/program/solidify scripts: references/quartus-cli.md
SignalTap setup and limitations: references/signaltap.md
PLL, DDS, frequency-counter, and DAC design patterns: references/design-patterns.md

Standard Workflow

Establish project context. Read the source PDF/DOCX or existing project. Extract the required module name, ports, clock, reset polarity, expected behavior, test method, and display requirements.
Scaffold or update the Quartus project. Use device EP4CE6F17C8, top entity from the lab requirement, Verilog source under src/, constraints in .qsf and .sdc, output under output_files, and local PowerShell scripts under scripts/.
Implement RTL conservatively. Keep the top-level port names compatible with the assignment. Synchronize mechanical switches/keys before using them across clock domains. Use PLL only when the measurement/design genuinely needs higher clock rates.
Assign pins. Use the MiniFPGA pin map reference. Add 3.3-V LVTTL I/O standards. Include the nCEO regular-I/O settings when needed for this board.
Compile and inspect timing. Run the build script or quartus_sh --flow compile <project>. Read the Timing Analyzer summary. If any required clock domain has negative slack, pipeline or lower the clock before programming.
Program live FPGA. After timing passes, use JTAG .sof programming. Confirm USB-Blaster [USB-0] and a successful Configuration succeeded message.
Solidify to configuration Flash when requested. Generate .jic for EPCS and program with indirect JTAG. Confirm erase, blank-check, program, and CRC verification all succeed.
Support waveform debugging. Open SignalTap from the project, configure signals, recompile, reprogram, then run acquisition. SignalTap configuration is part of the compiled design.

Reporting Back

Report exact status, not optimism: what was edited, whether compilation passed, worst slack if relevant, whether .sof download succeeded, whether .jic/Flash solidification succeeded, which physical pins to connect, and how to test the board.

MiniFPGA Quartus

Operating Rules

Use the command-line Quartus flow by default. The verified installation path is D:\Software\intelFPGA\18.1\quartus\bin64; still detect or accept another path if the user provides one.

Never program or solidify a build with negative setup/hold slack unless the user explicitly asks for a temporary unsafe test. Fix timing first, then download.

Do not invent unknown header pins. If the user has not provided external module pins, either ask for the header mapping or use clearly marked temporary pins such as LEDs for digital verification.

Preserve user changes in the worktree. Do not revert unrelated files.

Reference Routing

Read only what the task needs:

Board pins and fixed assignments: references/board-minifpga.md

Quartus compile/program/solidify scripts: references/quartus-cli.md

SignalTap setup and limitations: references/signaltap.md

PLL, DDS, frequency-counter, and DAC design patterns: references/design-patterns.md

Standard Workflow

Establish project context. Read the source PDF/DOCX or existing project. Extract the required module name, ports, clock, reset polarity, expected behavior, test method, and display requirements.

Scaffold or update the Quartus project. Use device EP4CE6F17C8, top entity from the lab requirement, Verilog source under src/, constraints in .qsf and .sdc, output under output_files, and local PowerShell scripts under scripts/.

Implement RTL conservatively. Keep the top-level port names compatible with the assignment. Synchronize mechanical switches/keys before using them across clock domains. Use PLL only when the measurement/design genuinely needs higher clock rates.

Assign pins. Use the MiniFPGA pin map reference. Add 3.3-V LVTTL I/O standards. Include the nCEO regular-I/O settings when needed for this board.

Compile and inspect timing. Run the build script or quartus_sh --flow compile <project>. Read the Timing Analyzer summary. If any required clock domain has negative slack, pipeline or lower the clock before programming.

Program live FPGA. After timing passes, use JTAG .sof programming. Confirm USB-Blaster [USB-0] and a successful Configuration succeeded message.

Solidify to configuration Flash when requested. Generate .jic for EPCS and program with indirect JTAG. Confirm erase, blank-check, program, and CRC verification all succeed.

Support waveform debugging. Open SignalTap from the project, configure signals, recompile, reprogram, then run acquisition. SignalTap configuration is part of the compiled design.

Reporting Back

minifpga-quartus