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Implement Milestone I sub-issues โ floating-point arithmetic lowering (SSE2/NEON/RV F+D extensions, FP register class, FP calling convention) and non-promotable memory (stack frame, SP-relative alloca/load/store, non-constant GEP) across all backends.
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| name | fp-memory |
| description | Implement Milestone I sub-issues โ floating-point arithmetic lowering (SSE2/NEON/RV F+D extensions, FP register class, FP calling convention) and non-promotable memory (stack frame, SP-relative alloca/load/store, non-constant GEP) across all backends. |
Use this skill to implement individual Milestone I sub-issues end-to-end.
All backends currently stub FP arithmetic (emit 0) and non-promotable memory (emit NOP). The regalloc does not distinguish integer vs. FP register classes. The infrastructure change needed first is a minimal register-class extension, then each backend gets its own PR.
Before per-backend FP work, llvm-codegen needs:
RegClass enum: Int and Float variants (add to isel.rs)VReg carries a RegClass field: VReg { id: u32, class: RegClass }MachineFunction::allocatable_fp_pregs: Vec<PReg> alongside the existing
allocatable_pregs (integer pool)allocate_registers dispatches to two separate linear-scan passes, one per
class, producing a combined RegAllocResultallocatable_fp_pregs in lower_functionThis infrastructure PR is the dependency for all FP sub-issues.
Branch: feat/milestone-i-regclass-infra
instructions.rs)ADDSD_RR, SUBSD_RR, MULSD_RR, DIVSD_RR, SQRTSD_R
ADDSS_RR, SUBSS_RR, MULSS_RR, DIVSS_RR, SQRTSS_R
XORPD_RR (for FNeg: xor with sign-bit mask)
UCOMISD_RR, UCOMISS_RR
CVTTSD2SI_RR, CVTSI2SD_RR, CVTTSS2SI_RR, CVTSI2SS_RR
MOVSD_LOAD_MR, MOVSD_STORE_RM (FP spill/reload)
MOVSS_LOAD_MR, MOVSS_STORE_RM
regs.rs)pub const XMM0: PReg = PReg(16); // through
pub const XMM15: PReg = PReg(31);
pub const FP_ALLOCATABLE: [PReg; 8] = [XMM0..XMM7]; // caller-saved
pub const FP_CALLEE_SAVED: [PReg; 8] = [XMM8..XMM15]; // Win64 only
abi.rs)ArgLocation with FpReg(PReg)lower.rs)InstrKind::FAdd with float ty โ emit ADDSS_RR dst, lhs, rhsInstrKind::FAdd with double ty โ emit ADDSD_RR dst, lhs, rhsXORPD_RR dst, src, sign_mask_constantRegClass::Floatencode.rs)0x66 + 0x0F + opcode byte66 0F 58 /rtests/fp_encode.rsfixtures/fp_add_f64.ll, etc.double add(double a, double b) { return a + b; } IR,
link, call with (1.5, 2.5), assert result is 4.0instructions.rs)FADD_RR, FSUB_RR, FMUL_RR, FDIV_RR, FNEG_R, FSQRT_R
FCMP_RR (sets flags; pair with FCSEL or B_COND)
FMOV_RR, FMOV_IMM
FCVTZS_RR, SCVTF_RR, UCVTF_RR (FP โ integer)
LDR_FP_SCALAR, STR_FP_SCALAR (FP spill/reload, distinct from existing LDR_FP)
regs.rs)AArch64 hardware shares the 32 V-registers between SIMD and scalar FP.
pub const D0: PReg = PReg(32); // through D31 = PReg(63)
pub const FP_ALLOCATABLE: [PReg; 16] = [D0..D7, D16..D23]; // caller-saved
pub const FP_CALLEE_SAVED: [PReg; 8] = [D8..D15];
abi.rs)classify_aapcs64_args to emit ArgLocation::FpReg for float typesencode.rs)ftype bits [23:22] selecting S/D0x1E202800 | (ftype<<22) | (Rm<<16) | (Rn<<5) | Rd0x1E203800 | ...; FMUL: 0x1E200800 | ...; FDIV: 0x1E201800 | ...0x1E214000 | (ftype<<22) | (Rn<<5) | Rd0x1E202000 | (ftype<<22) | (Rm<<16) | (Rn<<5) (Rd=0)tests/fp_encode.rsdouble add(double, double) matches clang AArch64 outputinstructions.rs)FADD_D, FSUB_D, FMUL_D, FDIV_D, FSQRT_D, FNEG_D
FADD_S, FSUB_S, FMUL_S, FDIV_S, FSQRT_S, FNEG_S
FMV_D_X, FMV_X_D, FMV_W_X, FMV_X_W (int โ FP reg transfer)
FCVT_D_W, FCVT_W_D, FCVT_D_WU, FCVT_WU_D (conversion)
FLD, FSD (FP load/store)
regs.rs)pub const F0: PReg = PReg(32); // through F31 = PReg(63)
pub const FP_ARG_REGS: [PReg; 8] = [F10..F17]; // fa0..fa7
pub const FP_ALLOCATABLE: [PReg; 12] = [F0..F7, F10..F17]; // ft0-7, fa0-7
pub const FP_CALLEE_SAVED: [PReg; 12] = [F8, F9, F18..F27]; // fs0-11
encode.rs)funct7 | rs2 | rs1 | funct3 | rd | opcodefunct7=0b0000001, opcode=0x53rm=0b111 (dynamic rounding mode) for all opsThis PR is independent of the FP register class infra โ can land first.
mem2reg promotes allocas that:
getelementptr with non-constant indices)When an alloca does NOT meet these criteria, the backend must:
All backends โ lower.rs:
frame_slots: HashMap<VReg, i32> to the lowering contextAlloca: call assign_frame_slot(size, align) โ returns i32 byte
offset; map dst_vreg โ offsetStore where ptr_vreg maps to a frame slot: emit SP-relative storeLoad where ptr_vreg maps to a frame slot: emit SP-relative loadGEP with constant index over a frame-slotted base: add offset to slotx86_64 โ stack frame:
SUB RSP, frame_size (aligned to 16)Store to frame slot: MOV [RBP-offset], srcLoad from frame slot: MOV dst, [RBP-offset]MOV_STORE_FP_RM (store to frame), MOV_LOAD_FP_MR (load)AArch64 โ stack frame:
STR src, [fp, #-offset] / LDR dst, [fp, #-offset]RISC-V โ stack frame:
ADDI sp, sp, -frame_size; SD ra, offset(sp)SD src, -offset(s0) / LD dst, -offset(s0)alloca_escapes_to_callee: alloca whose address is passed to an external
function; callee writes a value; after return, load must return that valuealloca_in_loop: alloca used across loop iterations (not promotable)struct_field_store_load: struct alloca with two field stores + loadsorigin/main: git fetch origin && git checkout -b feat/milestone-i-<slug> origin/maincargo test -p <crate> green before committingcargo test --workspace green before pushinggh pr review --comment summarizing findingsgh pr merge <N> --squashgh issue close <sub-issue-N>gh issue close 285; update #93 Status Snapshot