Generate a default `constraint/default.sdc` for a specified RTL top module by inspecting the RTL interface, run `make sta` in a Yosys/iEDA style synthesis and STA project, then analyze `result/` reports and produce key timing, area, power, and constraint findings with concrete timing-closure suggestions. Use when Codex is asked to prepare SDC for an RTL module, execute the local `make sta` flow, summarize STA results, or propose synthesis/STA remediation actions.
Use this skill when the user describes hardware behavior in natural language and needs a strict RTL delivery flow: derive a structured spec, plan the architecture, implement RTL, run lint, write a testbench, and complete behavioral simulation. Trigger it for module-level digital design tasks, interface/protocol decomposition, combinational or sequential RTL coding, TB scaffolding, waveform-driven debug, and regression-style validation with tools such as iverilog, verilator, or vvp. When using this skill, spawn a subagent to execute the bounded implementation and verification work, then integrate the result in the main agent.