analog-chip-design-agents

Distil append-only experiences.jsonl run records into per-domain knowledge.md summaries for the analog design agents. Use after enough runs accumulate to merge new convergence fixes, sizing recipes, PDK quirks, and tool flags into the Tier-2 knowledge file.

Analog circuit (schematic) design — topology selection, device sizing via gm/Id, biasing, schematic capture, pre-layout ERC, and design review. Use when designing an op-amp, comparator, bandgap, LDO, bias generator, or any analog block from a block specification through to a sign-off-ready schematic and netlist.

EDA tool detection, wrapper deployment, and MCP configuration for analog/mixed-signal + RF design environments. Use when setting up a workstation, verifying tool availability before a domain flow, or generating per-tool install scripts with TCL modulefiles.

Floorplan, generate matched devices, and place/route analog blocks with symmetry, shielding, and matching constraints to a clean, DRC-ready layout. Use when turning a sign-off-ready schematic into a GDS layout, or servicing a fix_request that repairs the layout after a DRC/LVS or parasitic-degradation failure.

Run DRC, LVS, antenna/ERC, and density/DFM checks on an analog layout and sign off a physically-clean GDS. Use when verifying a custom layout against the foundry rule deck and the source netlist, or re-validating after a custom-layout fix_request was serviced. Opens fix_requests routed to custom-layout on DRC/LVS failures.

Cross-domain loop orchestration for the analog/mixed-signal + RF design pipeline. Provides the fix_request protocol, iteration-cap logic, the authoritative design_state.json constraints schema, failure classification, and approval checkpoints. Use when driving the closed-loop spec↔circuit↔layout feedback cycle.

Solve the electromagnetics of an on-chip passive or antenna (inductor, transformer, transmission line, balun, antenna), extract a converged passive S-parameter model, and fit a lumped equivalent for circuit-level RF simulation. Use when building the passive model rf-design consumes, or to service an rf-design fix_request (route_to: em-modeling) by re-solving the passive. Loop-backs are stage-local (passivity/fit → meshing/geometry_definition); passivity is a hard gate; a fundamental geometry/stackup gap escalates.

Design and verify an RF/mmWave block (LNA, mixer, VCO, PLL, PA): topology selection and matching, S-parameter, harmonic-balance, Pnoise/PAC, IP3, and load-pull analyses, signed off against the RF spec table across corners. Use when designing or re-running an RF block. Loop-backs are stage-local first (spec/stability → topology_matching, convergence → harmonic_balance); when a cap is exhausted RF opens a cross-domain fix_request (circuit-design for device rework, em-modeling for a passive shortfall) and reads the EM-modeling passive model as a data dependency.

Qualify analog IP, assemble the mixed-signal top, define boundary/connect rules, run chip-level AMS simulation, and check power intent through integration sign-off. Use when integrating signed-off analog/RF blocks into a mixed-signal top, or re-validating after an integration fix. Opens fix_requests routed to custom-layout, circuit-design, or behavioral-modeling.

Run electromigration, IR-drop, ESD, latch-up, and aging (HCI/NBTI) analyses on a signed-off analog layout and sign off long-term reliability. Use when verifying that power/signal routing and devices survive the rated current, voltage, and lifetime, or re-validating after a custom-layout / circuit-design fix_request was serviced. Opens fix_requests routed to custom-layout (EM/IR) or circuit-design (ESD).

Characterize timing, power, and noise of a signed-off analog/mixed macro across PVT corners and generate validated Liberty (.lib) + behavioral models for downstream integration. Use when building the abstract views a chip-level / digital flow consumes, or re-running after a setup fix. Loop-backs are stage-local (model_validation → char_setup); a fundamental model gap escalates.

Run RC and coupling extraction on the verified layout and build a back-annotated post-layout netlist for sign-off simulation. Use when extracting parasitics from a physically-clean GDS, building the PEX netlist for post-layout sign-off, or flagging a layout for parasitic reduction.

Run post-PEX corner and Monte-Carlo simulation on the extracted netlist, re-verify specs against the pre-layout design, and gate tape-out. Use when closing a block's specs on the extracted netlist, quantifying parasitic degradation, or driving the tape-out approval gate. Opens fix_requests routed to custom-layout or circuit-design on post-layout spec loss.

Build mixed-signal testbenches, define connect rules, run analog-digital co-simulation and real-number-model regressions, and close functional coverage. Use when verifying an analog/mixed-signal block against its digital control across corners, or re-validating after a model/circuit fix. Opens fix_requests routed to behavioral-modeling or circuit-design.

Capture top-level analog/mixed-signal specs, budget noise/linearity/power across a signal chain, allocate per-block specifications, and assess feasibility before circuit design begins. Use when planning a receiver front-end, data-converter front-end, sensor AFE, PLL/clock, or PMIC from a system spec down to a per-block specification contract.

Author, compile, and validate analog behavioral models — Verilog-A, Verilog-AMS, VHDL-AMS, and SystemVerilog real-number models — plus the connect modules that bridge analog and digital domains. This is the analog-HDL core of the marketplace. Use when building a fast, accurate model of an analog block for AMS verification or system simulation.

Analog circuit simulation — testbench setup, DC operating point, AC, transient, noise, stability, PVT corners, and Monte-Carlo yield analysis, ending in electrical-spec sign-off. Use when verifying an analog block's specs across corners, debugging convergence, or closing Monte-Carlo yield on a SPICE netlist.