chisel-npu

Use when building the NPU FPGA bitstream for xc7k480tffg1156-2 — includes the squashed Vivado build flow (build_npu.tcl and build_npu_with_ila.tcl), bootstrap_project.tcl, the consolidated _apply_npu_topology.tcl BD library, ILA insertion, and bitstream configuration. Also use when modifying BD topology, RTL source (npu_ctrl_lite.v, npu_dma_master.v, npu_subsys.v), or Chisel top.sv regeneration.

Use when working with the Chisel NPU source code — ISA encoding, VALU, MMALU, NCoreBackend, register file, assembler (NpuAssembler), or Scala tests. Also use when regenerating top.sv, running sbt test, or understanding the ISA parameter notation (N-bits, L, K).

Use when testing, flashing, or debugging the xc7k480tffg1156-2 FPGA board — includes bringup_flash.py, program_flash.sh, serial console, 9 XDMA smoke tests, 6 MMALU compute tests, the u_npu_ila debugger core, and PCIe/DDR3 debugging. Also use for any question about the FPGA hardware bring-up flow or NPU validation on real hardware.