swangneu

Use when designing, choosing, or tuning a grid-forming inverter control law for a Simulink/Simscape model, or when a gfm-validation report shows design assumptions or controller parameters need revision. Covers droop, VSG/synchronverter, dVOC, PSC, virtual impedance, inner V/I loops on an LCL, multi-unit P/Q sharing, nominal current/protection envelope checks, and validation-feedback retuning. Produces a populated `gfm_params.m` parameter struct plus analytical predictions. Out of scope: running sim(), certification/grid-code compliance proof, bridge/PWM correctness, grid-following controllers.

Design or refactor AI harnesses, agent workflows, eval-fix loops, and self-improving coding systems using the EMD feedback pattern -- a symbolic generalization of PID control: Error (current failure), Memory (leaky history of recurring failures), Delta (change since last iteration). Use when adding structured iteration feedback, recurring-failure memory, trend/regression signals, stagnation handling, anti-windup guardrails, or architecture-aware decision routing to an iterative AI workflow. Ships a standalone Python reference implementation (scripts/emd_state.py).

Use when validating a grid-forming inverter Simulink or Simscape model against a gfm-design parameter struct or analytical prediction. Triggers include running sim(), checking logged P/Q/f/V/I signals, comparing simulation results to gfm_predict_steady_state, building validation reports, defining nominal/load-step/frequency/voltage/LVRT/FRT scenarios, and reviewing whether a GFM simulation supports the design assumptions. Companion to gfm-design; use this only after a model, logs, or explicit simulation-validation request exists.

Use when taking a power-supply or analog-circuit idea all the way from LTspice simulation to a verifiable KiCad project (schematic + PCB + footprints + ERC/DRC). Covers ADI/LTC µModule demo-board adaptation, ASC → KiCad conversion, BGA functional-pad footprints, 4-layer stackup conversion, input protection hardening, datasheet-driven pin verification, kicad-cli-driven verification, and the structural ASC ↔ KiCad netlist cross-check. Companion to any project-specific LTspice skill — use that one for simulation, this one for everything between sim and a clean DRC pass. Out of scope: gerber generation as an acceptance artifact, certification/compliance, mechanical/thermal proof, custom IC design.