Ejecuta cualquier Skill en Manus
con un clic

Ejecuta cualquier Skill en Manus con un clic

$pwd:

adc-analyzer

Name: Adc Analyzer
Author: Arcadia-1

// ADC characterization orchestrator in the analog-agents project. Takes simulated/measured ADC output, produces the standard specs bundle (SNDR/SFDR/THD/ENOB, INL/DNL, FOM, NTF where applicable) as a verifier-report, and hands off back to the design/sizing loop. TRIGGER when the user asks to characterize an ADC, extract ENOB/INL/DNL from dout/aout, compute Walden/Schreier FOM, analyze Σ-Δ NTF, or check thermal/jitter noise floors. For raw API usage (function names, arguments, imports) see the `adctoolbox-user-guide` skill shipped with the package.

Ejecutar en Manus

$ git log --oneline --stat

stars:23

forks:7

updated:28 de abril de 2026, 16:13

SKILL.md

readonly

name

adc-analyzer

description

ADC characterization orchestrator in the analog-agents project. Takes simulated/measured ADC output, produces the standard specs bundle (SNDR/SFDR/THD/ENOB, INL/DNL, FOM, NTF where applicable) as a verifier-report, and hands off back to the design/sizing loop. TRIGGER when the user asks to characterize an ADC, extract ENOB/INL/DNL from dout/aout, compute Walden/Schreier FOM, analyze Σ-Δ NTF, or check thermal/jitter noise floors. For raw API usage (function names, arguments, imports) see the `adctoolbox-user-guide` skill shipped with the package.

ADC Analyzer

You are the ADC characterization agent. Inputs: dout (digital codes) or aout (reconstructed analog), sample rate fs, input tone fin, resolution. Outputs: a structured spec report plus plots saved under verifier-reports/L2-performance/.

Backend is the adctoolbox package in analog-agents/.venv. All function-level questions ("which function takes what?", "flat vs submodule import") go to the adctoolbox-user-guide skill — do not re-document that here.

Scope boundaries

upstream (spectre skill): runs the simulation, produces the raw output stream
upstream (analog-verify skill): pre-sim review + DC/AC sanity — do not skip
this skill: post-conversion characterization only
downstream (optimizer skill): consumes SNDR/ENOB/FOM as an objective to minimize

Skip this skill for non-ADC analog blocks — those go to analog-verify.

Standard characterization flow

Always run in this order; stop and report the moment something fails.

Coherency check — confirm fin is at a coherent bin for the chosen N; if not, warn and pick a nearby coherent fin (see find_coherent_frequency in the user guide).
Spectrum + core specs — SNDR, SFDR, THD, ENOB, noise floor + FFT plot.
Linearity — INL/DNL from sine histogram (needs full-scale input covering all codes).
Error-domain analysis — only if the spectrum shows structure the specs don't explain (e.g., spurs, periodicity): error-by-phase, error PDF, autocorrelation.
FOMs & floors — Walden + Schreier; compare against thermal-noise and jitter limits; state whether the ADC is noise-, distortion-, or linearity-limited.

For SAR: add weight-calibration pass + radix analysis. For Σ-Δ: add ntf_analyzer.

Report layout

Write to verifier-reports/L2-performance/adc-<timestamp>.md, plots into <project>/output/plots/ or WORK/plots/. Keep numeric output in the markdown; push any waveform/density visualization into saved PNGs.

One table per concern: spec table (measured / target / margin / status), MOSFET op recap (if available from upstream), FOM table, noise-floor comparison. No prose beyond one-line callouts.

Handoff rules

Pass: report convergence to the orchestrator; do not re-dispatch designer.
Fail, iter < max_iter: dispatch analog-design in background with the failing specs, suggested causes from error-domain analysis, and iteration counter incremented.
Fail, iter ≥ max_iter: escalate to orchestrator with all reports attached.

adctoolbox-user-guide — full API routing: imports, flat vs submodule, examples, dashboards
adctoolbox-contributor-guide — only when editing the adctoolbox source itself
spectre — to (re-)run the simulation that feeds this skill
analog-verify — upstream pre-sim + L1 DC/AC gate
optimizer — downstream, if the failing spec needs a sizing sweep

related-skills.json

mismo repositorio

analog-netlist-crawl.md

from "Arcadia-1/analog-agents"

Crawl and analyze post-layout parasitic netlists without running SPICE. Answers "what's the effective resistance from node A to node B across this massive R mesh?", "inside the VREFN mesh, which device pins are electrically farthest apart?", "which nets have the worst coupling?", "where does settling bottleneck?" — by parsing the netlist, building a sparse graph, and solving the resistance Laplacian / summing the capacitance network. Format-agnostic: Calibre xRC mr_pp (.pex.netlist), Spectre flat, Spectre with subckt + include chain (.pex / .pxi splits), and Cadence calibreview bundles all produce identical kernel output. TRIGGER whenever the user shares a post-layout / extracted / parasitic netlist and asks about symmetry, parasitic C, parasitic R, coupling, driving-point resistance, within-net R distribution, pin-to-pin R, SAR CDAC analysis, comparator input impedance — even if they don't say "post-layout". Also trigger on filenames ending in .pex.netlist, .pxi, or mentions of xRC, Calibre extraction, RCC m

2026-05-0223

analog-verify.md

from "Arcadia-1/analog-agents"

Pre-simulation review and Spectre simulation verification for analog circuits. Reviews circuit netlist and testbench, runs simulation, produces margin report. Use after analog-design completes a netlist.

2026-04-2223

virtuoso-librarian.md

from "Arcadia-1/analog-agents"

Move, clone, package, archive, split, or reorganize Cadence Virtuoso cells and libraries at the design-data level. Use this skill whenever the user wants to: copy a TB to another library, reproduce a sim independently in a fresh library, hand off a design, prepare a tapeout archive, split one TB cell into several, promote a block between libraries, or enumerate a design's full reference hierarchy. Think of it as the "librarian" for your Virtuoso workspace — it knows which cells belong together, how to move them without breaking config bindings, and how to distinguish project cells from PDK / std-cell / analogLib references.

2026-04-2223

analog-evolve.md

from "Arcadia-1/analog-agents"

Self-evolution engine for analog-agents. Reviews completed design sessions to extract lessons, discover new anti-patterns, propose checklist additions, and refine agent prompts. Run after design convergence or project completion. TRIGGER on: "evolve", "what did we learn", "improve skills", "meta-review", "self-improve", or automatically at end of analog-pipeline.

2026-04-1623

analog-pipeline.md

from "Arcadia-1/analog-agents"

MANDATORY — MUST load this skill when the user mentions: OTA, ADC, PLL, comparator, bandgap, LDO, amplifier, opamp, or any analog/mixed-signal IC design task. Full analog design pipeline: spec -> architecture -> design -> verify -> deliver. Orchestrates analog-decompose, analog-behavioral, analog-design, analog-review, analog-verify, analog-integrate, and analog-wiki skills.

2026-04-1623

analog-audit.md

from "Arcadia-1/analog-agents"

Audit analog circuit netlists for correctness, quality, and risks. Supports both pre-layout (schematic) and post-layout (extracted) netlists. Post-layout mode filters massive parasitic netlists before auditing. Works without EDA. TRIGGER on: "audit", "review netlist", "check this circuit", "design review", "pre-layout", "post-layout", "post-sim", "extracted netlist".

2026-04-1623

package.json

"author": "Arcadia-1"

"repository": "Arcadia-1/analog-agents"

Abrir repositorio de GitHub Ver repositorios del creador

$ install --global

$ download --local

Ejecutar en Manus

$ useful --forSOC

Ingenieros electrónicos (excepto computadoras)Arquitectura e ingeniería17-2072L4

name

adc-analyzer

description

ADC Analyzer

Scope boundaries

upstream (spectre skill): runs the simulation, produces the raw output stream
upstream (analog-verify skill): pre-sim review + DC/AC sanity — do not skip
this skill: post-conversion characterization only
downstream (optimizer skill): consumes SNDR/ENOB/FOM as an objective to minimize

Skip this skill for non-ADC analog blocks — those go to analog-verify.

Standard characterization flow

Always run in this order; stop and report the moment something fails.

Coherency check — confirm fin is at a coherent bin for the chosen N; if not, warn and pick a nearby coherent fin (see find_coherent_frequency in the user guide).
Spectrum + core specs — SNDR, SFDR, THD, ENOB, noise floor + FFT plot.
Linearity — INL/DNL from sine histogram (needs full-scale input covering all codes).
Error-domain analysis — only if the spectrum shows structure the specs don't explain (e.g., spurs, periodicity): error-by-phase, error PDF, autocorrelation.
FOMs & floors — Walden + Schreier; compare against thermal-noise and jitter limits; state whether the ADC is noise-, distortion-, or linearity-limited.

For SAR: add weight-calibration pass + radix analysis. For Σ-Δ: add ntf_analyzer.

Report layout

One table per concern: spec table (measured / target / margin / status), MOSFET op recap (if available from upstream), FOM table, noise-floor comparison. No prose beyond one-line callouts.

Handoff rules

Pass: report convergence to the orchestrator; do not re-dispatch designer.
Fail, iter < max_iter: dispatch analog-design in background with the failing specs, suggested causes from error-domain analysis, and iteration counter incremented.
Fail, iter ≥ max_iter: escalate to orchestrator with all reports attached.

adc-analyzer

ADC Analyzer

Scope boundaries

Standard characterization flow

Report layout

Handoff rules

See also

ADC Analyzer

Scope boundaries

Standard characterization flow

Report layout

Handoff rules

See also

adc-analyzer

ADC Analyzer

Scope boundaries

Standard characterization flow

Report layout

Handoff rules

See also

Más de este repositorio

Más de este repositorio

ADC Analyzer

Scope boundaries

Standard characterization flow

Report layout

Handoff rules

See also