a5c-ai/babysitter - Page 50

jtag-swd-debug

Deep integration with JTAG/SWD debug probes for hardware-level debugging and flash programming

Langue du texte source : anglais

linker-script

GNU linker script generation and optimization for embedded systems. Expert skill for memory layout definition, section placement, multi-image linking, and memory protection configuration.

Langue du texte source : anglais

memory-analysis

Embedded memory analysis, optimization, and leak detection

Langue du texte source : anglais

misra-c-analysis

MISRA C compliance checking and static analysis integration

Langue du texte source : anglais

motor-control

Motor control algorithms and driver implementation

Langue du texte source : anglais

nordic-nrf

Nordic Semiconductor nRF5x/nRF Connect SDK expertise

Langue du texte source : anglais

ota-firmware-update

Over-the-air firmware update implementation expertise for embedded systems. Expert skill for delta updates, image signing, update protocols, partition management, and rollback mechanisms.

Langue du texte source : anglais

power-profiler

Power consumption measurement and analysis expertise for embedded systems. Integrates with power analyzer tools to measure, profile, and optimize power consumption in battery-powered and energy-efficient designs.

Langue du texte source : anglais

protocol-analyzer

Serial protocol analysis and debugging for common embedded interfaces (I2C, SPI, UART)

Langue du texte source : anglais

scope-logic-analyzer

Test equipment integration for signal analysis (oscilloscope and logic analyzer)

Langue du texte source : anglais

stm32-hal

STMicroelectronics STM32 HAL and Low-Level driver expertise

Langue du texte source : anglais

unity-ceedling-test

Embedded unit testing with Unity framework and CMock

Langue du texte source : anglais

usb-stack

USB device and host stack implementation expertise

Langue du texte source : anglais

wireless-protocols

Embedded wireless protocol implementation (LoRa, Zigbee, Thread, Matter)

Langue du texte source : anglais

zephyr-rtos

Specialized skill for Zephyr RTOS development and configuration

Langue du texte source : anglais

axi-protocol

Expert skill for AMBA AXI protocol implementation and verification in FPGA designs

Langue du texte source : anglais

cdc-analysis

Specialized skill for clock domain crossing analysis and synchronizer design in FPGA designs

Langue du texte source : anglais

formal-verification

Formal property verification and model checking skill for FPGA designs

Langue du texte source : anglais

fpga-debugging

On-chip debugging skill with ILA, VIO, and related FPGA debug tools

Langue du texte source : anglais

fsm-design

Specialized skill for finite state machine design and optimization in FPGAs

Langue du texte source : anglais

hdl-simulation

Multi-simulator expertise for functional verification of FPGA designs

Langue du texte source : anglais

hls-cpp-to-rtl

Expert skill for C/C++ to RTL conversion using High-Level Synthesis tools

Langue du texte source : anglais

ip-core-management

Vendor IP core configuration and integration expertise for FPGA designs

Langue du texte source : anglais

memory-interfaces

Expert skill for on-chip and external memory interface design in FPGAs

Langue du texte source : anglais

place-and-route

Expert skill for FPGA place and route optimization and physical implementation

Langue du texte source : anglais

power-analysis

FPGA power estimation and optimization skill for low-power design

Langue du texte source : anglais

rtl-linting

RTL code quality checking and linting. Runs lint rules, identifies synthesis issues, detects inferred latches, and generates lint reports with waivers.

Langue du texte source : anglais

sva-assertions

Specialized skill for creating and debugging SystemVerilog assertions for FPGA verification

Langue du texte source : anglais

synthesis-optimization

Expertise in RTL optimization for FPGA synthesis tools. Analyzes synthesis reports, applies attributes, and guides resource inference for optimal QoR.

Langue du texte source : anglais

uvm-methodology

Deep expertise in Universal Verification Methodology (IEEE 1800.2) for FPGA verification

Langue du texte source : anglais

verilog-sv-language

Expert-level Verilog and SystemVerilog knowledge following IEEE 1800 standards. Generates synthesizable RTL code with proper coding styles and constructs.

Langue du texte source : anglais

vhdl-language

Deep expertise in VHDL language constructs, IEEE 1076 standard compliance, and synthesis coding guidelines. Expert skill for generating synthesizable VHDL code.

Langue du texte source : anglais

cublas-cudnn

Expert integration with NVIDIA GPU-accelerated math libraries. Configure cuBLAS tensor core operations, generate cuBLAS GEMM calls, integrate cuDNN layers, handle algorithm selection, and support mixed-precision operations.

Langue du texte source : anglais

cuda-debugging

Expert skill for GPU debugging using CUDA-GDB and NVIDIA Compute Sanitizer. Detect memory errors, race conditions, uninitialized memory access, validate atomic operations, analyze kernel synchronization issues, and generate debugging reports with…

Langue du texte source : anglais

cuda-graphs

Expert skill for CUDA Graph capture and optimization for reduced launch overhead. Capture CUDA operations into graphs, instantiate and execute graph instances, update graph node parameters, profile graph vs stream execution, design graph-friendly kernel…

Langue du texte source : anglais

cuda-toolkit

Deep integration with NVIDIA CUDA toolkit for kernel development, compilation, and debugging. Execute nvcc compilation with optimization flags analysis, generate and validate CUDA kernel code, analyze PTX/SASS assembly output, and configure execution…

Langue du texte source : anglais

cutlass-triton

High-performance kernel template libraries and DSLs. Generate CUTLASS GEMM configurations, implement Triton kernel definitions, configure epilogue operations, tune tile sizes and warp arrangements, and benchmark against cuBLAS.

Langue du texte source : anglais

gpu-benchmarking

Expert skill for automated GPU performance benchmarking and regression detection. Design micro-benchmarks, measure kernel execution time with CUDA events, calculate achieved vs theoretical performance, generate comparison reports, detect regressions in CI/CD,…

Langue du texte source : anglais

gpu-memory-analysis

Specialized skill for GPU memory hierarchy analysis and optimization. Analyze memory access patterns, detect bank conflicts, optimize cache utilization, profile global memory bandwidth, and generate optimized memory access code patterns.

Langue du texte source : anglais

hip-rocm

AMD HIP and ROCm ecosystem for cross-platform GPU development. Execute hipify conversion tools, generate HIP-compatible kernel code, handle CUDA/HIP API differences, configure ROCm toolchain, and profile with rocprof.

Langue du texte source : anglais