arch-hdl-lang

Write, modify, debug, and verify ARCH HDL code. Use when working with `.arch` files, ARCH language constructs such as module/fsm/fifo/ram/arbiter/pipeline/bus/thread/testbench, ARCH compiler errors, SystemVerilog generation from ARCH, ARCH simulation, formal checks, or ARCH coding guidance.

Write, modify, debug, and verify HARC verification code. Use when working with `.harc` files, HARC tests, transactions, constraints, covergroups, scoreboards, transactors, sequencers, properties, reference models, `harc check`, `harc sim`, or HARC-to-DUT integration with ARCH or SystemVerilog.