asic-ai-workflows

Extract a source-grounded, AI-readable textual design view from HDL source, parser output, MCP tool output, or model reasoning. Use this skill when the user needs Verilog, SystemVerilog, VHDL, or proprietary hardware description language normalized into a reusable design view for downstream analysis flows such as timing, lint, CDC, RDC, formal planning, or DV planning. Prefer UHDM text for SystemVerilog/Verilog when available, AST JSON when UHDM is not available, and explicit model-derived views only when no tool evidence exists.

Analyze an HDL design view or visible RTL for pre-synthesis timing risk by estimating combinational logic depth on register-to-register and boundary timing paths. Use this skill when the user already has a UHDM text dump, AST JSON, source-grounded textual design view, or small visible RTL block and asks for critical paths, deep combinational logic, reg-to-reg timing risk, or pre-synthesis timing feedback. This skill is analysis-only; use an HDL-design-view extraction skill or flow when parser/tool/MCP selection, source-language normalization, or design-view generation is required.

Read an approved microarchitecture specification and emit synthesizable SystemVerilog with requirement traceability. Use this skill whenever the flow moves from block architecture into concrete RTL implementation.

Review synthesizable SystemVerilog for static RTL issues such as inferred latches, reset mismatches, width hazards, and multi-driver structure. Use this skill whenever generated RTL needs a deterministic front-end lint audit before CDC, RDC, or timing review.

Normalize a block-level design brief into deterministic requirements, explicit PPA targets, and open intake questions. Use this skill whenever the user provides high-level microarchitectural intent and the workflow must capture power, performance, and area before specification or RTL work begins.

Assemble normalized requirements, the microarchitecture spec, generated RTL, and static audit summaries into one front-end handoff package. Use this skill whenever the block-level RTL planning flow needs one deterministic output that can feed downstream DV planning.

Turn normalized block requirements into a Markdown microarchitecture specification with requirement traceability and targeted diagrams. Use this skill whenever the workflow needs a deterministic architecture document before RTL generation.

Audit RTL for reset-domain crossing hazards that are separate from clock-domain crossings. Use this skill whenever a design has multiple resets, asynchronous reset release behavior, or reset-bridged control paths that need structured review.

Convert a short block-level design-intent brief plus provided RTL context into a deterministic list of DV objectives. Use this skill whenever the user wants to turn design intent into verification targets, expected behaviors, or block-level success criteria before choosing tests, assertions, or coverage.

Assemble a block-level DV plan from objectives, RTL surface data, UVM test planning, SVA candidates, functional coverage, and optional CDC or timing risk reports. Use this skill whenever the user wants one final structured DV plan with deterministic IDs, explicit unresolved items, and a UVM-centric environment recommendation.

Build a block-level functional coverage plan from objectives and RTL surface information. Use this skill whenever the user wants deterministic coverpoints, crosses, and exclusions tied back to explicit verification objectives.

Extract the block-level verification surface from provided Verilog or SystemVerilog RTL. Use this skill whenever the user wants a structured summary of clocks, resets, interfaces, state-visible behaviors, observability points, and unresolved verification gaps before building a DV plan.

Plan assertion candidates for a block-level DV effort from objectives and RTL evidence. Use this skill whenever the user wants reset, protocol, state, data-integrity, or error property candidates that are grounded in visible behavior rather than speculative timing assumptions.

Build a block-level, UVM-centric DV test matrix from objectives and RTL surface information. Use this skill whenever the user wants a greenfield UVM environment recommendation, prioritized test scenarios, and justified monitors, scoreboards, reference models, or virtual sequences.

Lint Verilog or SystemVerilog RTL for clock domain crossing (CDC) violations. Use this skill whenever the user asks to check for CDC issues, find unsynchronized crossings, review multi-clock designs, audit clock domain safety, or look for metastability risks in HDL code. Also trigger when the user pastes or points to an RTL module with multiple clocks and asks for a review, even if they don't explicitly say "CDC". This is a pre-EDA lint that catches issues early, before formal CDC tools like Spyglass or Meridian run.