kh7272723-star

Digital front-end RTL design assistant for Verilog/SystemVerilog. MUST use this skill for ANY RTL coding task, module interface design, FSM design, ready/valid or req/ack handshakes, FIFO/pipeline/arbiter/counter patterns, testbench generation, timing explanation, lint/code review, simulation debug, or bug triage. Even if the user doesn't mention "skill" or "RTL" explicitly, trigger this for any digital hardware design work including synthesis-aware coding, CDC handling, protocol implementation (AXI/APB/AHB/AXI-Stream), clock gating, interrupt controllers, DMA engines, and multi-module subsystem design.