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Inspect the specification, existing SKiDL/KiCad sources, component datasheets, power tree, I/O definitions, and required deliverables. If inputs are incomplete, create a short design brief with operating conditions and clearly labeled assumptions.
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Define min/nominal/max electrical conditions, startup/fault states, source/load impedances, accuracy/noise/bandwidth goals, environmental limits, and acceptance criteria before selecting values.
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Select exact manufacturer part numbers when behavior, pinout, package, model, or lifecycle matters. Verify symbol pin numbers, unit mapping, footprint, polarity, ratings, and model provenance against primary documentation.
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Build explicit SKiDL nets and interfaces. Add stable tag= values, named rails, connectors/test points at external boundaries, decoupling, unused-unit treatment, and intentional no-connect or ERC exceptions with rationale.
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Keep formulas and derived values near named parameters. Check worst-case stress and tolerance, not only nominal arithmetic. Do not reuse cookbook values without validating them against the chosen part and operating conditions.
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Compile and generate the standard logical artifacts from the repository root:
uv run python -m py_compile <input.py>
uv run python skills/circuit-design/scripts/skidl_runner.py <input.py> -o <outputs/>
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Generate a KiCad 9 schematic with the repository exporter when its topology is supported:
uv run python skills/circuit-design/scripts/kicad_sch_export.py <input.py> -o <outputs/>
Current SKiDL also provides generate_schematic() for KiCad schematics. Prefer that native path for general circuits when it produces a readable result, and treat the repository exporter as a tested compatibility path rather than claiming universal coverage.
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If kicad-cli is available, validate the generated schematic independently:
kicad-cli sch erc --exit-code-violations --format json -o <outputs/reports/project-kicad-erc.json> <outputs/kicad/project/project.kicad_sch>
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Run only the analyses required by the specification. Use models whose source, version, pin order, and applicability are recorded:
uv run python skills/circuit-design/scripts/pyspice_sim.py <input.py> -o <outputs/> --dc
uv run python skills/circuit-design/scripts/pyspice_sim.py <input.py> -o <outputs/> --ac
uv run python skills/circuit-design/scripts/pyspice_sim.py <input.py> -o <outputs/> --tran
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Compare ERC and simulation results with explicit acceptance criteria. Report unmodeled behavior, convergence changes, datasheet dependencies, remaining warnings, and downstream PCB/layout/thermal/EMC work.
