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Analyze PCB layout and suggest optimizations (traces, copper balance, thermal, vias)
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Basé sur la classification professionnelle SOC
Full PCB verification loop using local kicad-cli (DRC + 3D render + gerbers)
Create a new Claude Code skill for this project. Use when you need to add a new skill, improve an existing skill, or convert a workflow into a reusable skill.
Verifies that every PCB pad-to-net assignment matches the manufacturer datasheet pin specifications. Use when changing board.py/routing.py/footprints.py, after GPIO remapping, before releases, or when adding new components. Automated guard against wiring errors like unconnected VBUS, wrong pin assignments, or missing GND connections.
Design intent adversary — cross-checks GPIO, nets, power chains, signal paths across firmware/schematic/PCB/datasheet sources to find lost connections and inconsistencies
Analyze a DFM report and fix all issues in the PCB generation scripts
Run DFM guard tests and add new regression tests after fixing PCB issues
| name | pcb-optimize |
| model | claude-opus-4-7 |
| description | Analyze PCB layout and suggest optimizations (traces, copper balance, thermal, vias) |
| disable-model-invocation | true |
| allowed-tools | Bash, Read, Grep, Glob, Edit, Write |
Analyze the generated .kicad_pcb file for layout quality and suggest optimizations across five categories: trace length, copper balance, thermal vias, via count, and crosstalk risk.
cd /Users/pierrejonnycau/Documents/WORKS/esp32-emu-turbo
python3 scripts/pcb_optimize.py
Optionally pass a custom PCB path:
python3 scripts/pcb_optimize.py path/to/custom.kicad_pcb
The script produces a report with five modules, each scored 0-20 (total 100):
| Module | What it checks | Threshold |
|---|---|---|
| Trace Length | Total length per net, single segment length | >80mm net, >40mm segment |
| Copper Balance | F.Cu vs B.Cu trace distribution | >50% difference |
| Thermal Vias | GND vias near power ICs (IP5306, AMS1117, PAM8403) | min 3 vias within 5mm |
| Via Optimization | Vias per net count | >4 vias/net |
| Parallel Traces | Crosstalk risk between data signals | gap < 3x trace width |
Based on the report, edit the routing or board layout:
# Edit routing traces
$EDITOR scripts/generate_pcb/routing.py
# Edit component placement
$EDITOR scripts/generate_pcb/board.py
python3 -m scripts.generate_pcb hardware/kicad
python3 scripts/pcb_optimize.py
Repeat until the score is satisfactory.
After running the analysis, present results as:
| Module | Score | Issues | Status |
|---|---|---|---|
| Trace Length | ?/20 | ? flags | OK/WARN |
| Copper Balance | ?/20 | F.Cu ?% / B.Cu ?% | OK/WARN |
| Thermal Vias | ?/20 | ? ICs under-viad | OK/WARN |
| Via Optimization | ?/20 | ? nets with excess vias | OK/WARN |
| Parallel Traces | ?/20 | ? crosstalk pairs | OK/WARN |
| Overall | ?/100 |
scripts/pcb_optimize.py -- PCB layout optimization analyzerscripts/generate_pcb/routing.py -- Trace routing definitionsscripts/generate_pcb/board.py -- Component placement and board generationscripts/generate_pcb/primitives.py -- Net IDs and PCB element helpersscripts/drc_check.py -- DRC check (complementary, manufacturing rules)hardware/kicad/esp32-emu-turbo.kicad_pcb -- Generated PCB file (analysis target)