Guides the development of a new Open Logic entity through a mandatory six-phase workflow (proposal → entity declaration → RTL → testbench → documentation → integration & verification) with a user-review checkpoint at the end of every phase. Use when the user asks to create, develop, design, contribute, add, or implement a new VHDL entity, area, or module for the Open Logic library.
Always use when user asks to create, generate, draw, or design a diagram, flowchart, architecture diagram, ER diagram, sequence diagram, class diagram, network diagram, mockup, wireframe, or UI sketch, or mentions draw.io, drawio, drawoi, .drawio files, or diagram export to PNG/SVG/PDF.
Always use when the user asks to create, generate, draw, or design a timing diagram, waveform, signal-level protocol diagram (SPI, I2C, UART, AXI handshake, clock-with-enable, request/acknowledge), bitfield / register-layout diagram, or logic-schematic diagram, or mentions WaveDrom, WaveJSON, wavedrom-cli, `.json5` waveform files, or signal-export to SVG/PNG/PDF.
Debug failing FPGA simulation tests by analyzing UVVM logs, capturing waveforms, and querying signal data with the wavequery tool. Use when a VUnit test fails, a simulation produces unexpected results, or the user asks to debug, troubleshoot, or investigate an FPGA module, testbench, or simulation issue. Covers root cause analysis, fix identification, and iterative re-verification.
Guides FPGA module development through a mandatory six-phase workflow covering requirements, architecture, design description, verification planning, RTL implementation, and testbench implementation using VUnit and UVVM. Use when the user asks to create, develop, design, verify, or test an FPGA module, IP core, or VHDL component in this repository.
Debug failing or unexpected Open Logic VUnit testbenches by analysing the simulator log, capturing waveforms, and querying signal data with the wavequery tool. Use when a VUnit test fails, a simulation produces unexpected results, or the user asks to debug, troubleshoot, or investigate an Open Logic entity, testbench, or simulation issue.