tscircuit

name	tscircuit
description	Build, modify, and debug tscircuit designs.
allowed-tools	Read, Write, Grep, Glob, Bash

Examples

• ./examples

Getting started

1. Clarify requirements (if not already given)

   • Board form factor / size constraints
   • Power sources and voltage rails
   • I/O: connectors, headers, mounting holes, mechanical constraints
   • Target manufacturer constraints (trace/space, assembly, supplier)
   • <trace/> will produce netLabels when the traces cannot be connected.

2. Choose a starting point

   • If the repo is not a tscircuit project, recommend:
     • Install CLI, then tsci init to bootstrap a project.
   • If a form-factor template is appropriate (Arduino Shield, Raspberry Pi HAT, etc.), prefer @tscircuit/common templates.

Standard workflow (schematic placement/debug loop)

Before writing code, inspect ./examples and use the closest matching example as your starting point. Use this sequence for schematic tasks that require checker-driven placement cleanup:

1. Create or update the schematic with explicit structure/grouping as requested.

2. Respect user constraints.

3. Before running placement checks:

   • remove all manual schX and schY from schematic components
   • remove all manual schWidth and schHeight overrides

4. Run

   • tsc --noEmit.

5. Run:

   • tsci check schematic-placement

6. Add only coordinates explicitly returned by the check to the circuit.

7. Fix reported issues in this order, rerunning the check after each fix:

   • VerboseSchematicNetLabel
   • PinHeaderSchematicBoxTooWide
   • GenericSchematicBoxTooWide
   • SchematicBoxInnerLabelCollision
   • CapacitorSymbolHorizontal
   • SchematicPinPaddingToEdgeTooLarge
   • DiodeResistorNotAligned
   • ComponentOverlap
   • SchematicBoxHasALotOfSurroundingWhitespace
   • ComponentNetLabelCollision
   • ComponentBoxNetLabelCollision
   • NetLabelCollision

8. Rerun tsci check schematic-placement after each applied fix; each run may resolve multiple violations and may also expose new ones.

9. Continue only with user-requested next steps after the loop is clean.

Placement constraints

• Do not add schX, schY, schWidth, or schHeight manually unless directly instructed by tsci check schematic-placement.

Syntax

• ./SYNTAX.md

Export.

• Run tsci build.
• Run tsci snapshot.

Builtin Elements

• <analogsimulation />
• <battery />
• <board />
• <cadassembly />
• <cadmodel />
• <capacitor />
• <chip />
• <connector />
• <constraint />
• <copperpour />
• <coppertext />
• <courtyardcircle />
• <courtyardoutline />
• <courtyardpill />
• <courtyardrect />
• <crystal />
• <currentsource />
• <cutout />
• <diode />
• <fabricationnotedimension />
• <fabricationnotepath />
• <fabricationnoterect />
• <fabricationnotetext />
• <fiducial />
• <footprint />
• <fuse />
• <group />
• <hole />
• <inductor />
• <jumper />
• <led />
• <mosfet />
• <mountedboard />
• <net />
• <netalias />
• <opamp />
• <panel />
• <pcbkeepout />
• <pcbnotedimension />
• <pcbnoteline />
• <pcbnotepath />
• <pcbnoterect />
• <pcbnotetext />
• <pcbtrace />
• <pinheader />
• <pinout />
• <platedhole />
• <port />
• <potentiometer />
• <pushbutton />
• <resistor />
• <resonator />
• <schematicarc />
• <schematicbox />
• <schematiccell />
• <schematiccircle />
• <schematicline />
• <schematicpath />
• <schematicrect />
• <schematicrow />
• <schematicsection />
• <schematictable />
• <schematictext />
• <silkscreencircle />
• <silkscreenline />
• <silkscreenpath />
• <silkscreenrect />
• <silkscreentext />
• <smtpad />
• <solderjumper />
• <subcircuit />
• <subpanel />
• <switch />
• <symbol />
• <testpoint />
• <trace />
• <tracehint />
• <transistor />
• <via />
• <voltageprobe />
• <voltagesource />