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verilog-lint-root-cause-csv
Use for cross-level Verilog lint root-cause analysis from prepared RTL, slices, and filelist inputs.
Codex または Claude でインストール この Prompt をコピーして Codex、Claude、または他のアシスタントに貼り付けると、Skill ページを確認してインストールできます。
メニュー
Use for cross-level Verilog lint root-cause analysis from prepared RTL, slices, and filelist inputs.
Codex または Claude でインストール この Prompt をコピーして Codex、Claude、または他のアシスタントに貼り付けると、Skill ページを確認してインストールできます。
SOC 職業分類に基づく
Use this skill when the user provides Verilog/SystemVerilog source files or a source directory plus a top module, and wants a concise Chinese JSON diagnosis for hierarchical constant-propagation defects caused by parent-module constant pins or named wires that pollute child-module inputs, internal wires, and outputs across multiple levels, using the bundled trace_constant_propagation.py engine and then separating likely real defects from design-intended constants.
Use this skill when the user provides Verilog/SystemVerilog source files or a source directory plus a top module, and wants a concise Chinese JSON diagnosis for unreachable procedural branches, static dead-code conditions, or logic that disappears before/after Yosys proc/opt, especially cases where for-loop unfolding or constant loop variables make if/case branches impossible.
Use this skill when the user provides Verilog/SystemVerilog source files and a lint report, and wants the lint rows first pre-grouped by same source line and same violation description, then triaged into severe defect, general defect, or false positive, plus missed-defect discovery mapped to rules in the built-in custom knowledge base under skills/verilog-lint-triage/references, while batching IEEE standard lookups by semantic topic instead of per lint row, plus a separate standards-based code-only diagnosis section grounded in IEEE built-in references, with the final result written to a timestamped JSON file.
Use this skill when the user provides Verilog/SystemVerilog code plus a lint warning and wants a specific, code-aware repair recommendation in a concise Chinese JSON report rather than a generic lint-tool message, especially incomplete case coverage warnings such as W69 where the agent must identify missing case items or propose a concrete default branch.
| name | verilog-lint-root-cause-csv |
| description | Use for cross-level Verilog lint root-cause analysis from prepared RTL, slices, and filelist inputs. |
Require these three prepared design-evidence paths:
rtl/ source directory;slices/ directory;filelist.f.Also require one exact draft CSV output path from the outer workflow. Treat it as an output target, not as design evidence.
Do not read the original source archive, original lint CSV, hierarchy work directory, or slice policy. Do not preprocess inputs, classify modules, build slices, sort, validate, publish, or create timestamped reports. The outer workflow owns those operations.
Read slices/coverage.json first. Then process the exclusive lint scopes in
this order without merging their lint.csv files:
level1 -> level2 -> level3 -> level4 -> isolated
For each scope:
context.json for module source paths, parameters, ports, and child
instances;lint.csv for exclusively owned alerts;filelist.f for compile order and macros;slices/hierarchy_tree.txt for active instance context;rtl/<source_file> at source_line and inspect the
relevant enclosing construct before assigning its root cause, grouping, fix,
or false-positive status;message_id or contents alone; if the
corresponding source and relevant context have not been inspected, do not
finalize that row;hierarchy field as equivalent instances of one
source warning, not as multiple leaf violations;After completing each scope, write its analyzed rows into the one supplied draft while retaining all rows from earlier scopes. Do not create separate per-scope reports. After all five scopes are present, consolidate that same draft into the global result: merge cross-level rows when they share the same defect mechanism and concrete repair strategy, make their category fields consistent, and keep every leaf row exactly once.
Treat a lint finding as a false positive when the reported code is intentional, conforms to the project design intent, and requires no RTL change. A rule may correctly recognize a code pattern and still be a false positive when it cannot account for that design intent. If the RTL requires a change, use a normal root; if the design intent cannot be confirmed, continue the analysis instead of marking the finding as a false positive.
Maintain one global defect-class view across every scope. Assign the same
root_id when findings share the same underlying defect mechanism and can be
resolved by the same concrete repair strategy:
Use parent_root_id only to record direct causal dependence between two
distinct normal roots. Treat a root as derived only when source, hierarchy, or
signal-flow evidence shows that the parent defect causes or enables the child
defect, while the child still has a different defect mechanism or requires a
different concrete repair.
Apply these rules:
root_id instead of creating a parent-child pair;误报 to a parent;parent_root_id=/ unless one direct causal
direction is supported;/ rather than guessing;root_note; state the child-specific repair and any required repair order in
fix_suggestion.For example, violations caused directly by one combinationally generated clock and cleared by replacing it with a clock enable belong to one root. Create a derived child only if a separate downstream clock-generation construct is caused by that root and still requires its own RTL change; point that child to the generated-clock root.
Map leaf fields directly from each scope lint.csv:
leaf_violation_id = vio_id
leaf_violation_note = message_id:contents
Preserve message_id and contents exactly.
Write or revise only the exact draft path supplied by the outer workflow. Keep the same path throughout all revisions. Write exactly these columns in order:
root_id,root_note,fix_suggestion,root_file_path,root_file_start,root_file_end,parent_root_id,leaf_violation_id,leaf_violation_note
Apply these rules:
root_001;root_note, fix_suggestion, and parent_root_id values on
every row sharing a normal root ID;root_note and fix_suggestion in concise Chinese;rtl/ directory for
root_file_path (for example, core/a/foo.v) and record the concrete defect
occurrence for that leaf; never collapse nested paths to a basename;/ for an independent root's parent_root_id;root_id=误报, explain in root_note why the
code is intentional and needs no RTL change, and use / for
fix_suggestion and parent_root_id;Before finishing, perform a second source-based pass over every draft row. For
each row, locate its original entry in the corresponding scope lint.csv,
reopen rtl/<source_file> at source_line, inspect the relevant enclosing
construct, and reopen the recorded root_file_path and root range when they
differ from the leaf location. Never approve a row from the lint text or draft
text alone. Confirm:
vio_id occurs exactly once and both leaf fields are exact;Do not finish after the first draft. Revise the same draft path until this second-pass review is complete, then return control to the outer workflow.