ariklapid

Use before changing RTL, DV collateral, constraints, backend artifacts, HDL parsers, or hardware workflow fixtures when the task needs evidence before implementation.

Use when manually syncing or pulling changes from the original upstream Superpowers repository into ASIC Superpowers while preserving ASIC-specific skills, plugin identity, evals, and metadata.

Use when starting any session that may involve RTL, ASIC design, Design Verification, Physical Design / Backend, SystemVerilog, constraints, EDA tool output, or hardware verification evidence.

You MUST use this before any creative work - creating features, building components, adding functionality, or modifying behavior. Explores user intent, requirements and design before implementation.

Use when completing tasks, implementing major features, or before merging to verify work meets requirements

Use when about to claim work is complete, fixed, or passing, before committing or creating PRs - requires running verification commands and confirming output before making any success claims; evidence before assertions always

Use when you have a spec or requirements for a multi-step task, before touching code

Use pyslang-mcp for compiler-backed Verilog and SystemVerilog context. Trigger this skill for RTL, HDL, Verilog, SystemVerilog, module, interface, package, .sv, .svh, .v, .vh, or .f filelist analysis, review, debugging, coding, refactoring, hierarchy inspection, diagnostics triage, symbol lookup, include/define investigation, and design-unit summaries. Skip it for unrelated languages or trivial text searches where rg is sufficient.