Build simulation testbenches for IO Ring / mixed-signal designs in Cadence Virtuoso. Automates the full flow: symbol export -> pin redistribution -> testbench creation -> DUT placement -> LLM-driven pin classification -> source/load placement with label-based wiring. Use this skill whenever the user wants to create a simulation testbench, classify IO pins, place stimulus/load on a DUT, or run the sim_flow pipeline for any design. Also use when the user mentions "sim flow", "testbench", "TB setup", "pin classification", "source placement", or "stimulus generation" in the context of Virtuoso simulation.
2026-05-11