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Chooses block/tile dimensions, warp counts, pipeline stages, and L2-aware block grouping for GPU kernels (Triton/CUDA/HIP). Use when autotuning matmul-like kernels, tuning occupancy, or aligning tile geometry with M/N/K and NVIDIA vs AMD thread models.
Codex または Claude でインストール この Prompt をコピーして Codex、Claude、または他のアシスタントに貼り付けると、Skill ページを確認してインストールできます。
SOC 職業分類に基づく
Optimize fused cross-entropy loss kernels in Triton for NVIDIA and AMD GPUs. Covers fused log-softmax + NLL, online log-sum-exp, and large vocabulary handling. Use when writing or optimizing cross-entropy, label-smoothed CE, or similar loss kernels.
Optimize FlashAttention-style fused attention kernels in Triton for NVIDIA and AMD GPUs. Covers online softmax, tiled QK/AV GEMM, causal masking, and memory-efficient attention. Use when writing or optimizing self-attention, cross-attention, or any QKV attention kernel.
Optimize dense matrix multiplication (GEMM) kernels in Triton for NVIDIA and AMD GPUs. Covers tiled blocking, L2 cache grouping, tensor core utilization, and dual-platform autotune. Use when writing or optimizing matmul, linear layers, or any GEMM-based kernel.
Optimize RMS Normalization kernels in Triton for NVIDIA and AMD GPUs. Covers row-parallel reduction, vectorized loads, warp shuffle patterns, and rsqrt usage. Use when writing or optimizing RMSNorm, LayerNorm, or similar normalization kernels.
Optimize Rotary Position Embedding (RoPE) kernels in Triton for NVIDIA and AMD GPUs. Covers interleaved/sequential layouts, sincos precomputation, and multi-row processing. Use when writing or optimizing RoPE, position embeddings, or rotary transformations.
Optimize fused softmax kernels in Triton for NVIDIA and AMD GPUs. Covers online max/sum reduction, multi-row processing, numerical stability, and warp-level patterns. Use when writing or optimizing softmax, log-softmax, or similar row-wise normalization kernels.
| name | gpu-opt-tier1-block-tiling |
| description | Chooses block/tile dimensions, warp counts, pipeline stages, and L2-aware block grouping for GPU kernels (Triton/CUDA/HIP). Use when autotuning matmul-like kernels, tuning occupancy, or aligning tile geometry with M/N/K and NVIDIA vs AMD thread models. |
This skill is Tier 1 in AutoKernel's tiered optimization playbook: fix launch geometry before memory micro-optimizations.
BLOCK_K is often ≥16 (NVIDIA WMMA/WGMMA) or ≥32 (AMD MFMA on CDNA).BLOCK_N helps B reuse in row layouts; taller BLOCK_M helps A reuse. Balance against register/SMEM pressure.<128): prefer smaller tiles (64×64, 64×128) so enough blocks exist to fill the GPU.BLOCK_K can amortize loads but raises SMEM/regs; validate occupancy.num_warps=4 ⇒ 256 threads per block.num_stages≥2 on NVIDIA. On HIP/ROCm, num_stages must be ≥1 (0 is invalid).num_stages + large tiles can spill registers; co-tune with num_warps.GROUP_SIZE_M consecutive block-rows before advancing along N to reuse B slices in L2.| Vendor | BLOCK_M×N×K (examples) | num_warps | num_stages | Notes |
|---|---|---|---|---|
| NVIDIA | 64–256 each axis, K often 32–64 | 2, 4, 8 | 2–5 | WGMMA kernels may need arch-specific caps |
| AMD | 64–256, K often 32 | 2, 4, 8 (×64 threads/warp) | 1–3 | Add waves_per_eu (e.g. 2–8) when supported |
waves_per_eu hints: 2–4 when compute-bound, 4–8 when memory-bound (empirical starting points).GROUP_SIZE_M=8; shrink M/N when grid is too coarse.num_warps 4 or 8; always include at least one 64×64×32 candidate when occupancy is poor.(BLOCK_M, BLOCK_N, BLOCK_K) candidates × num_warps × num_stages (respect HIP num_stages≥1).GROUP_SIZE_M (e.g. 4/8/16) for GEMM-like kernels with large inner dimension.