oh-my-fpga

Author a correct Vivado XDC timing constraint set from scratch — primary clocks, generated (derived) clocks, input/output delays, and timing exceptions (clock groups / false paths / multicycle paths) — for a design that has no constraints yet, or whose constraints are incomplete (unconstrained ports, missing generated clocks, unrelated async clocks reported as failing paths). Invoke when the user says: "write constraints", "author xdc", "set up timing constraints", "no constraints yet", "constrain my clocks", "add input/output delays", "my clocks are asynchronous / I need clock groups", or whenever check_timing / report_timing_summary reports unconstrained clocks, ports, or combinational endpoints. This is the FIRST step before any timing-closure or signoff work — WNS/TNS numbers are meaningless until the design is correctly constrained. Requires the SynthPilot MCP server connected to an OPEN Vivado session with the Tcl server running (test_connection must pass) and a project that elaborates and synthesizes.

Analyze and reduce dynamic and static power on a Xilinx Vivado design (total power, junction temperature, thermal margin). Use when the user says "reduce power", "power optimization", "lower power consumption", "power report", "report_power", "too hot / junction temp too high", "battery / thermal budget", "cut dynamic power", "static/leakage power", or asks why a design draws too much current. Requires the SynthPilot MCP server with Vivado open and the tcl_server.tcl TCP bridge running.

Generate a bitstream and program a Xilinx FPGA over JTAG, or build an MCS image and burn it into SPI/BPI configuration flash for power-on boot. Invoke when the user says "program the board", "generate bitstream", "flash the device", "download to FPGA", "burn the flash", "load my design onto the board", "make a .mcs / .bit", or "why won't my board come up after power cycle". Covers the full hand-off from a routed implementation to live silicon: DRC + route + timing sign-off gating, .bit generation, hardware-server / JTAG connect, volatile JTAG download, and non-volatile flash programming (generate_mcs + add_flash_configuration + program_flash). Requires the SynthPilot MCP server with Vivado running and the Tcl server connected; flash / JTAG steps additionally require a physical board cabled to the host (or reachable through a remote hw_server).

Audit and resolve clock-domain-crossing (CDC) risks on a design: enumerate every clock crossing, classify each by structure (synchronizer present/absent, single-bit vs bus, async reset, reconvergence), and apply the smallest safe fix (synchronizer RTL, set_clock_groups / set_max_delay -datapath_only / set_bus_skew constraints) without ever waiving a real crossing. Invoke when the user says "cdc analysis", "check clock domain crossings", "metastability review", "are my async crossings safe", "audit clock crossings", "fix CDC violations", "report_cdc is showing critical", "do I need a synchronizer here", or asks about gray-code, handshake, async FIFO, or reset-domain-crossing (RDC) safety. Requires the SynthPilot MCP server with Vivado open and the Tcl server running (TCP:9999); CDC reporting needs an elaborated or synthesized design.

Measure RTL simulation code coverage (statement / branch / condition) and iteratively close it toward an explicit target by adding targeted testbench stimulus. Use when the user asks "what is my code coverage", "how much is covered", "coverage closure", "improve coverage to N%", "which lines aren't tested", "are there untested branches", or wants a sign-off-grade coverage report before tape-out / merge. Requires the SynthPilot MCP server with Vivado + the Tcl server running (xsim/xelab/xcrg, validated on Vivado 2024.2). PRO-tier tool sim_get_coverage. This is a methodology playbook, not code: it tells the AI which real SynthPilot tools to call, in what order, and how to decide what to do with the numbers.

Drive a Xilinx FPGA design end-to-end through the complete build flow: RTL -> simulation -> synthesis -> implementation -> bitstream, with a verification gate after every stage so a downstream stage never runs on an upstream stage that silently regressed. Invoke this skill when the user says "rtl to bitstream", "end to end", "full flow", "run everything", "build the whole thing", "take this design all the way to a .bit", "complete build", or asks to drive a project from source files to a programmed/exportable bitstream in one orchestrated pass. Requires the SynthPilot MCP server connected to an open Vivado session with the Tcl server (tcl_server.tcl on TCP:9999) running. This is the ORCHESTRATION playbook: it sequences the real flow tools, gates each stage on fresh tool evidence, stops on the first real failure, and hands off to the specialist skills (timing-closure, cdc-analysis, lint, simulation-debug) instead of trying to fix violations itself.

Insert/connect an ILA (Integrated Logic Analyzer), program the board, arm a trigger, and read back captured waveforms on real FPGA hardware. Use when the user says "debug on hardware", "insert ILA", "capture waveform on the board", "the design works in sim but fails on the board", "trigger when X happens on hardware", "probe a signal live", "read the ILA", or wants to observe live silicon behavior via JTAG. Covers the full loop: mark/insert debug cores -> re-implement -> bitstream -> connect hardware server -> program with .ltx probes -> set trigger -> arm -> capture -> read CSV. Requires the SynthPilot MCP server with Vivado open and tcl_server.tcl running, plus a physical JTAG-connected board and a running hw_server (hardware server).

Run RTL lint / methodology checks and triage each violation into a real fix vs a justified, documented waiver. Use when the user says "lint my RTL", "code quality", "review my RTL", "check my Verilog/VHDL", "any latches / unintended latches", "clean up warnings before synthesis", "is my design lint-clean", or asks for a code-quality / methodology report on an FPGA design. Requires the SynthPilot MCP server (Xilinx Vivado running with the Tcl server connected on TCP:9999). Methodology-stage checks additionally require an open synthesized design (open_synthesized_design / open_implemented_design).

Produce a one-page FPGA design-health scorecard (QoR: timing, area, power, congestion, clocking, DRC/methodology). Invoke when the user asks for a "design health" check, a "QoR" report, "quality of results", a "scorecard", "how good is my design", "is this ready for signoff", or wants a single consolidated read on timing/area/power/congestion after synthesis or implementation. Requires the SynthPilot MCP server (Vivado open with the Tcl server running on TCP:9999). This is a READ-ONLY measurement-and-grading playbook: it gathers fresh tool evidence, grades each axis, and reports — it does not modify constraints, RTL, or strategy.

Bring up a behavioral (RTL) simulation end-to-end: stand up or fix a testbench, compile (xvlog/xvhdl), elaborate (xelab), run (xsim), and methodically diagnose compile errors, elaboration failures, $fatal/assertion failures, X-propagation, and hangs. Use when the user says "simulate this", "run the testbench", "set up simulation", "my sim fails / hangs / shows X", "why does my testbench not pass", "add a testbench and verify the DUT", or "debug this RTL in simulation". Requires the SynthPilot MCP server (AI -> server.py -> TCP:9999 -> tcl_server.tcl running inside an open Vivado session). This is BEHAVIORAL sim only (no gate-level/timing sim); it does NOT prove timing closure or signoff. Measure (compile log / sim log / probe) before changing anything, classify the failure, apply the smallest safe fix, then re-run.

Close FPGA timing on a Vivado design driven by the SynthPilot MCP — iterate synthesis/implementation, diagnose critical paths, and apply the safest constraint/strategy fix until worst negative slack (WNS) and total negative slack (TNS) reach ≥ 0. Use when the user wants to close timing, fix negative WNS/TNS, resolve setup/hold violations, or asks why a design "doesn't meet timing". Requires the SynthPilot MCP (Vivado + Tcl server on :9999).

Diagnose and reduce FPGA resource/area pressure when a design is too big for the part. Use when the user says the design is "running out of LUTs", "too big for the part", "over 100% utilization", "won't fit", "out of BRAM/DSP/FF", "reduce utilization", "shrink area", "implementation failed: placement infeasible / overutilized", or asks to fit a design into a smaller/cheaper device. Requires the SynthPilot MCP server (AI-controlled Xilinx Vivado) with the Tcl server running inside an open Vivado session and a project loaded.

Stand up a Zynq-7000 PS7-based SoC block design (Processing System bring-up). Invoke when the user says "build a zynq soc", "ps7", "zynq bring up", "add a processing system", "PS-PL design", "bring up the ARM cores", "wire AXI GP/HP to the PL", "generate the bd wrapper for a Zynq", or asks to create / configure / validate a Zynq-7000 block design (FCLK, DDR, MIO/UART/GPIO, AXI interconnect, address map, wrapper). Requires the SynthPilot MCP server (AI-driven Vivado control) with Vivado open and the tcl_server.tcl TCP bridge running, and a PRO/MAX license (Block Design tools are gated). Zynq-7000 (PS7) only — NOT Zynq UltraScale+ MPSoC (use the mpsoc skill). Stop conditions: stop and ASK on unknown hardware-critical config (DDR part / board / target FCLK on a bare part); stop and HAND OFF on timing/DRC that fails after correct constraints; declare DONE only when bd_validate_design is clean AND post-implementation report_timing_summary (setup WNS/TNS >= 0 AND hold/min-delay >= 0), check_timing (no unconstrained