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Pin-to-net mapping auditor -- verifies that every IC pin in the schematic is connected to the correct net, matched against a pin map source of truth (CSV, datasheet table, or Python dict). Critical for BGA/QFN devices where swap errors are invisible to DRC/ERC.
Codex または Claude でインストール この Prompt をコピーして Codex、Claude、または他のアシスタントに貼り付けると、Skill ページを確認してインストールできます。
Create, import, analyze, or resume an end-to-end Circuit Weaver electronic design with durable project state. Load the canonical workflow from skills/circuit-weaver/SKILL.md. Use kicad for one-off file inspection, bom for sourcing, and design-wizard only when explicitly requested.
Use only for an explicitly requested step-by-step Circuit Weaver questionnaire. Load the canonical workflow from skills/design-wizard/SKILL.md; use circuit-weaver for ordinary automatic new-design requests.
Route non-critical nets on a real KiCad PCB or Specctra DSN through Circuit Weaver's fail-closed Freerouting integration. Use after placement and net-class setup when the user requests autorouting, a validated SES session, routing diagnostics, or post-route cleanup. Keep critical power, RF, clock, crystal, switching, and differential nets manual.
Generate KiCad schematics from a Circuit Weaver design.yaml or a project's own checked-in generator. Use for large, repetitive, or machine-synchronized designs. Prefer the Circuit Weaver CLI unless the project actually contains and documents its own generation scripts.
Design and verify professional multi-sheet KiCad hierarchies generated from Circuit Weaver functional sections. Use when adding, splitting, renaming, or reviewing schematic sheets, cross-sheet interfaces, root symbols, sheet ownership, or final hierarchy ERC.
Review Circuit Weaver's exhaustive placement proposal and apply approved SVG coordinates to a real electrically annotated KiCad PCB. Use after schematic generation for placement optimization, official-reference review, interactive SVG editing, strict reference reconciliation, and PCB placement handoff. Do not treat review artifacts as fabrication data.
SOC 職業分類に基づく
| name | kicad-pinmap |
| description | Pin-to-net mapping auditor -- verifies that every IC pin in the schematic is connected to the correct net, matched against a pin map source of truth (CSV, datasheet table, or Python dict). Critical for BGA/QFN devices where swap errors are invisible to DRC/ERC. |
ERC and DRC cannot catch a swapped pin. A power pin on a signal net passes all automated checks but produces a dead or damaged board. The only defense is comparing the schematic pin-to-net assignment against the datasheet pinout table.
# scripts/pin_maps.py
DEVICE_PINMAP = {
"A1": "GND",
"A2": "VDD_1V8",
"A3": "SPI_CLK",
"B1": "RESET_N",
"C4": "__NC__", # explicitly no-connect
}
Sources (in priority order):
kicad skill and retain the per-component
pin/net data as analysis.json.scripts/audit_pinmap.py
exists.Unmapped pins should get no-connect markers rather than floating unconnected. Floating digital inputs can cause latch-up or undefined behavior.
Flag any IC below 80% mapped. No-connect pins count as mapped.
| IC ref | Package | Total pins | Mapped | NC | Coverage |
|---|---|---|---|---|---|
| (fill in) |
SOT-23 transistors: BCE, BEC, EBC, and CBE orderings all exist for NPN BJTs;
GDS, GSD, SGD for N-MOSFETs. The KiCad symbol lib_id suffix encodes an assumed
pinout. Verify against the actual MPN's datasheet -- especially when no MPN is set.
Multi-unit ICs: Op-amp and gate packages with a shared VCC/GND unit. Ensure the power unit is placed and connected -- a missing power unit causes an ERC warning that can be overlooked.
Active-low signals: Verify RESET_N, CS_N, OE_N are driven with the correct polarity. A high-true signal on an active-low input means always-asserted.