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Use when writing, reading, or reviewing .ato files. Triggers on "what interface for X", "how to connect Y", choosing between interface types, parameter constraints, tolerance syntax, or atopile design patterns.
Codex または Claude でインストール この Prompt をコピーして Codex、Claude、または他のアシスタントに貼り付けると、Skill ページを確認してインストールできます。
SOC 職業分類に基づく
Use when designing a new board or modifying board-level architecture in atopile. Triggers on new board creation, connector wiring, power rail routing, MCU peripheral assignment, or composing packages into a board.
Use when building, validating, or debugging atopile projects. Triggers on build errors, "ato build", solver failures, "no parts found", package management, creating parts from JLCPCB, or debugging connectivity issues.
Use when adding a new IC, component, or subcircuit to an atopile project. Triggers on creating atopile packages, sourcing parts, vendoring an existing package, or deciding whether to make a shared package vs. inline in a board. Also use when you see ato create part or are about to write a new .ato driver module.
Use when reviewing or completing an atopile package or board design. Triggers on design review, pre-commit check, "is this ready", quality audit, finishing a package implementation, or verifying a design before build.
Use when renaming or refactoring components in .ato files that have existing PCB layout placements. Triggers on "layout broken", "components at origin", "lost placement after rename", "relink layout", or any .ato refactor that changes component names or module structure.
Use when working with .ato files and you need semantic code intelligence — hover info, diagnostics, go-to-definition, find-references, or symbol inspection. Triggers on questions like "what type is this", "what members does X have", "where is X defined", "what uses Y", checking for parse errors, or understanding atopile module/interface signatures.
| name | ato-language |
| description | Use when writing, reading, or reviewing .ato files. Triggers on "what interface for X", "how to connect Y", choosing between interface types, parameter constraints, tolerance syntax, or atopile design patterns. |
mcp__atopile-lsp__get_hover): pass file path + line + character to get full member lists, usage examples, and docs for any symbol. Always hover on an import or type before writing code that uses it.mcp__atopile-lsp__get_definition): jump to where a module/interface is defined -- use to read library source.mcp__atopile-lsp__get_references): find all usages of a symbol across the project.mcp__atopile-lsp__get_diagnostics): parse errors and type mismatches for a file.ato <command> --help for full flags. Use ato --help for the command list.find_packages / inspect_package MCP tools or the ato registry at packages.atopile.io.See the lsp skill for full LSP-over-MCP usage.
| Need | Use | Not |
|---|---|---|
| Power rail (VCC/GND pair) | ElectricPower | Electrical |
| Digital logic (GPIO, CS, EN, INT) | ElectricLogic | Electrical |
| Raw copper (single net) | Electrical | -- |
| I2C bus | I2C | two ElectricLogic |
| SPI bus | SPI | individual ElectricLogic |
| Analog signal (continuous, not binary) | ElectricSignal | ElectricLogic |
Key judgment calls:
ElectricLogic has a .reference (power rail) that MUST be connected -- this sets the logic level. Forgetting it causes silent build failures.Capacitor has a .power member (ElectricPower) for direct power rail connection, AND .unnamed[0]/.unnamed[1] for pin-level wiring. Use .power when decoupling a rail; use .unnamed[] when wiring between arbitrary nets (e.g. bootstrap cap between BTST and SW).Resistor only has .unnamed[0]/.unnamed[1] -- no named pins.ato build -- solver: picks parts, evaluates assertions, generates BOM, updates layoutato build --open -- launches KiCad after buildato create part -- generate component .ato from JLCPCBato dependencies add / ato dependencies remove -- manage package depsRun ato <command> --help for full flags. See the build-and-test skill for the full build/debug workflow.
10kohm finds zero parts (0% tolerance). Always use 10kohm +/- 5% or a range like 1kohm to 1.1kohm..reference.hv.Resistor and Inductor use unnamed[0]/unnamed[1], not named pins. Capacitor also has .power as an ElectricPower shortcut.package = "0402": constrains footprint only, not voltage or power rating. Always add assert X.max_voltage >= ... separately.within for bilateral ranges, is for exact match, >=/<= for bounds. Use assert X within 10V +/- 5% not assert X is 10V.~>): requires #pragma experiment("BRIDGE_CONNECT"). The module must have the can_bridge trait (Resistor, Capacitor, Inductor have it).#pragma experiment("FOR_LOOP")._ (e.g. _nt_acp, _cregn). External code accessing _-prefixed members is a code smell — the module's public interface should be sufficient.curl to grab the PDF from the manufacturer's website (ti.com, analog.com, st.com, microchip.com — prefer manufacturer over distributors) and save to a local datasheets/ directory (e.g. <manufacturer>_<part>_datasheet.pdf). Also grab the application note if one exists (_appnote.pdf).assert — this makes designs reconfigurable (change one parameter, solver checks everything downstream) and self-documenting (the assertion IS the design rationale).48kV for a K-factor) so formulas are recognizable alongside the datasheet.Every module must have clear documentation written while the design context is fresh:
# --- Section Name --- headers.assert should explain what it checks and where the threshold comes from (datasheet section, calculation, etc.).Documentation quality is a review gate — if a future agent can't use the module from its docs alone, the docs aren't good enough.
See design-patterns.md for idiomatic patterns extracted from production driver code — decoupling, for-loops, voltage dividers, pull-ups, Kelvin sense taps, component locking, datasheet formula encoding, submodule decomposition, config pins, reset handling, and I2C addressing.