mio210

Verilog/SystemVerilog RTL implementation, review, linting, synthesis-oriented debugging, testbench generation, and ASIC flow troubleshooting. Use when the user is working on concrete RTL or verification tasks: writing or modifying .v/.sv modules, reviewing synthesizable logic, generating directed/SystemVerilog/UVM testbenches, fixing lint/synthesis/timing/CDC/reset/DFT issues, or asking ASIC implementation-flow questions tied to RTL, constraints, or EDA reports. Do not use for general electronics, CPU architecture theory, non-RTL programming, vague chip-industry questions, or FPGA/EDA discussion without Verilog/SystemVerilog, synthesis, verification, timing, CDC, DFT, or ASIC-flow work.