メニュー
Execute delay-model validation gates against HPWL baselines. Use when evaluating model consistency, running Gate-0 contract checks, building Gate-1 bucketed scorecards, performing wirelength-aware correlation checks, or deciding readiness for active optimization.
Codex または Claude でインストール この Prompt をコピーして Codex、Claude、または他のアシスタントに貼り付けると、Skill ページを確認してインストールできます。
SOC 職業分類に基づく
Creates and refines academic presentations from research papers. Use this skill for tasks involving the conversion of scientific or technical documents into slide decks for conferences, seminars, lectures, thesis defenses, or academic reviews. Supports beamer LaTeX (.tex), PowerPoint (.pptx), and Markdown output formats.
Run a full EDA research chain from knowledge exploration and paper triage to idea debate, hypothesis experiment design, implementation, git versioning, validation, and retrospective. Use when the user requests an end-to-end EDA research workflow rather than a single isolated execution step.
Audit and refine academic manuscripts for structure, terminology consistency, LaTeX hygiene, and high-signal grammar fixes. Use this skill for theses, papers, proposals, and technical reports when the task is manuscript writing rather than experiment execution.
Diagnose and implement backside-routing realization paths, including targeted reroute, local DEF/OpenDB patching, and OpenROAD-backed net-level rerouter bring-up, when theory predicts benefit but the current flow does not realize BM2/BM1 usage.
Audit whether the local BSPDN physical contract is coherent across paper assumptions, GT3 tech collateral, layer/via topology, and current flow policy before promotion or expensive attribution experiments.
Manage and standardize project conda environment usage as an auxiliary utility skill, including env discovery, package availability checks, explicit env selection, and reproducible `conda run -n ...` integration for scripts and workflows.
| name | delay-model-gate-evaluator |
| description | Execute delay-model validation gates against HPWL baselines. Use when evaluating model consistency, running Gate-0 contract checks, building Gate-1 bucketed scorecards, performing wirelength-aware correlation checks, or deciding readiness for active optimization. |
Run these checks before promoting model changes into placement/CTS optimization.
<merged_or_unified_tsv>: Path to a merged or unified TSV file, for example data/merged_asap7_delay_v2.tsv or data/unified_timing_run03.tsv.<tag>: Descriptive run identifier such as run03_lr1e-3 or v2_bspdn_baseline. Use one naming scheme consistently across gates.ROOT=/mnt/research/Hu_Jiang/Students/Fang_Donghao/TAMU-ASAP07-BSPDN-BPR-V0.00
cd "$ROOT"
python3 scripts/debug/check_delay_model_contract.py \
--input-tsv <merged_or_unified_tsv> \
--delta-sign back_minus_front \
--min-sign-acc 0.60 \
--out-prefix slurm_logs/04_delay_modeling/<tag>.contract
Use --strict for CI-style hard fail.
If Gate-0 fails: Check the contract output first. If sign accuracy is below the threshold, inspect the worst-performing net groups for data quality issues such as missing features, outlier wirelengths, or inconsistent labels. Re-train or filter the input TSV before proceeding.
python3 scripts/debug/bucketed_delay_model_scorecard.py \
--input-tsv <merged_or_unified_tsv> \
--delta-sign back_minus_front \
--out-prefix slurm_logs/04_delay_modeling/<tag>.bucketed
If promotion criteria are not met: Do not proceed to active optimization. Iterate on the delay model instead by reviewing feature engineering, checking training-data coverage for underperforming buckets, and re-running both gates after the update.
Load references/metric_contract.md before interpreting results.