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Verify JLCPCB pick-and-place alignment for all bottom-side ICs and connectors. Checks CPL rotation, position corrections, and pin-to-net assignments. Use before any JLCPCB PCBA order or after changing CPL/rotation/position parameters.
Codex または Claude でインストール この Prompt をコピーして Codex、Claude、または他のアシスタントに貼り付けると、Skill ページを確認してインストールできます。
SOC 職業分類に基づく
Full PCB verification loop using local kicad-cli (DRC + 3D render + gerbers)
Create a new Claude Code skill for this project. Use when you need to add a new skill, improve an existing skill, or convert a workflow into a reusable skill.
Verifies that every PCB pad-to-net assignment matches the manufacturer datasheet pin specifications. Use when changing board.py/routing.py/footprints.py, after GPIO remapping, before releases, or when adding new components. Automated guard against wiring errors like unconnected VBUS, wrong pin assignments, or missing GND connections.
Design intent adversary — cross-checks GPIO, nets, power chains, signal paths across firmware/schematic/PCB/datasheet sources to find lost connections and inconsistencies
Analyze a DFM report and fix all issues in the PCB generation scripts
Run DFM guard tests and add new regression tests after fixing PCB issues
| name | jlcpcb-alignment |
| model | claude-opus-4-7 |
| description | Verify JLCPCB pick-and-place alignment for all bottom-side ICs and connectors. Checks CPL rotation, position corrections, and pin-to-net assignments. Use before any JLCPCB PCBA order or after changing CPL/rotation/position parameters. |
| disable-model-invocation | true |
| allowed-tools | Bash, Read, Grep, Glob |
Runs three verification passes on all 7 bottom-side ICs/connectors to ensure the JLCPCB pick-and-place machine will correctly align every component.
| Ref | Package | Pins | Key Risk |
|---|---|---|---|
| U1 | ESP32-S3-WROOM-1 | 41 | +3.62mm Y position correction |
| U2 | IP5306 ESOP-8 | 9 | Exposed pad, asymmetric |
| U3 | AMS1117 SOT-223 | 4 | Tab pad, asymmetric |
| U5 | PAM8403 SOP-16 | 16 | 90deg pre-rotation + override |
| J1 | USB-C 16-pin | 16 | -1.3mm Y position correction |
| J4 | FPC 40-pin | 42 | -2.66mm X position correction |
| U6 | Micro SD TF-01A | 13 | Asymmetric shield pads |
cd /Users/pierrejonnycau/Documents/WORKS/esp32-emu-turbo
python3 -c "
import sys
sys.path.insert(0, 'scripts')
from verify_dfm_v2 import test_batch_pin_alignment, test_batch_pin_net_assignment, PASS, FAIL
test_batch_pin_alignment()
test_batch_pin_net_assignment()
print(f'\nResults: {PASS} passed, {FAIL} failed')
sys.exit(1 if FAIL else 0)
"
This runs three test categories:
rotate(cpl_rot) -> mirror -> translate matches rotate(kicad_rot) -> mirror -> translate for every pin. Max pin error must be < 0.1mm.cpl_pos == board_pos + correction for each component. Catches wrong/missing corrections.scripts/generate_pcb/jlcpcb_export.py:
_JLCPCB_ROT_OVERRIDES for per-ref overrides_JLCPCB_ROT_CORRECTIONS for per-footprint pattern corrections_JLCPCB_POS_CORRECTIONS.make verify-fast # Full DFM suite (64 tests, ~1.5s)
The test uses the rotate -> mirror -> translate convention (matching get_pads() and routing._compute_pads()):
footprints.FOOTPRINTS[name][0]("B")rotate(kicad_rot) -> mirror_X -> translate(board_pos)rotate(cpl_rot) -> mirror_X -> translate(board_pos)Using board_pos (not CPL pos) for translation isolates the rotation check from position corrections.
scripts/verify_dfm_v2.py — test_batch_pin_alignment() and test_batch_pin_net_assignment()scripts/generate_pcb/jlcpcb_export.py — rotation/position correctionsscripts/generate_pcb/footprints.py — pad definitions (ground truth model)scripts/generate_pcb/routing.py — _compute_pads() (PCB file convention)release_jlcpcb/cpl.csv — CPL data sent to JLCPCB