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Analyze pad-to-pad distances to detect spacing violations before DFM upload
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| name | pad-analysis |
| description | Analyze pad-to-pad distances to detect spacing violations before DFM upload |
Analyze PCB pad-to-pad and pad-to-via edge distances to detect spacing violations.
Argument: Optional threshold in mm (default 0.15). Example: --threshold 0.20
The script reports ALL close pairs, but many are intentional:
Always filter results by net before acting on them.
cd /Users/pierrejonnycau/Documents/WORKS/esp32-emu-turbo
python3 scripts/analyze_pad_distances.py $ARGUMENTS
If no arguments provided, use default threshold:
python3 scripts/analyze_pad_distances.py --threshold 0.15
From the output, create a categorized table:
| Pair | Layer | Gap (mm) | Same Net? | Verdict |
|---|---|---|---|---|
| U1:1 ↔ C3:1 | F.Cu | 0.08 | No | VIOLATION |
| J4:5 ↔ via | B.Cu | 0.00 | Yes | OK (intentional) |
Filter out same-net pairs. Focus on:
For each real violation, identify the fix location:
| Issue Type | Fix File | Fix Action |
|---|---|---|
| Pad-to-pad too close | scripts/generate_pcb/board.py | Move component in _component_placeholders() |
| Via-to-pad too close | scripts/generate_pcb/routing.py | Move via position |
| Mounting hole clearance | scripts/generate_pcb/board.py | Increase hole-to-component gap |
Print a summary:
scripts/analyze_pad_distances.py — Main analysis scriptscripts/generate_pcb/board.py — Component placement (fix positions here)scripts/generate_pcb/routing.py — Via/trace positions (fix routing here)Full PCB verification loop using local kicad-cli (DRC + 3D render + gerbers)
Create a new Claude Code skill for this project. Use when you need to add a new skill, improve an existing skill, or convert a workflow into a reusable skill.
Verifies that every PCB pad-to-net assignment matches the manufacturer datasheet pin specifications. Use when changing board.py/routing.py/footprints.py, after GPIO remapping, before releases, or when adding new components. Automated guard against wiring errors like unconnected VBUS, wrong pin assignments, or missing GND connections.
Design intent adversary — cross-checks GPIO, nets, power chains, signal paths across firmware/schematic/PCB/datasheet sources to find lost connections and inconsistencies
Analyze a DFM report and fix all issues in the PCB generation scripts
Run DFM guard tests and add new regression tests after fixing PCB issues