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Extract RTL ports, generate instances/wrappers/top modules, and track interface changes through snapshots and integration configs. Use for generated SoC top-level integration and port-change maintenance.
Codex または Claude でインストール この Prompt をコピーして Codex、Claude、または他のアシスタントに貼り付けると、Skill ページを確認してインストールできます。
SOC 職業分類に基づく
Create and operate canonical SoC project/module scaffolds through registered MCP tools for filelists, lint, compile, simulation, regression, coverage, and synthesis. Use for SoC project setup and any EDA Make-target execution.
Close stale multi-stage SoC delivery evidence for a router-selected merge or signoff packet. Use only when vibe-soc-loop delegates final architecture, doc, RTL, verification, synthesis, integration, or PD closure; do not use for ordinary dev iterations.
Route one-sentence vibe_soc feature, RTL, integration, verification, synthesis, register, CRG, low-power, or PD requests into the smallest safe Loop execution packet. Use for SoC work that needs task classification, MCP selection, pipeline state, or delivery closure.
Generate Synopsys .db technology or stub libraries for early synthesis and link. Use when converting Liberty .lib to .db with lc_shell, or when creating a minimal black-box Liberty/.db from a Verilog top module port list.
Prepare and run local-default OpenROAD-flow-scripts physical-design handoff for silicon-crew SoC projects. Use when Codex needs to generate ORFS config/SDC under pd/openroad, run synth/floorplan/place/cts/route/finish/all stages through the default local ORFS path or explicit container backends, summarize OpenROAD reports/results, or connect vibe_soc-style RTL projects to OpenROAD.
Convert reviewed clock/reset Excel design tables into Draw.io and Excalidraw topology diagrams. Use for CRG source, mux, divider, OCC, ICG, and reset-chain visualization.
| name | soc-integrate |
| description | Extract RTL ports, generate instances/wrappers/top modules, and track interface changes through snapshots and integration configs. Use for generated SoC top-level integration and port-change maintenance. |
Use the registered soc-integrate MCP server; do not invoke the Python CLI as a fallback.
Tools:
soc_extract, soc_instantiate, soc_wrap, soc_csvsoc_integrate, soc_extract_map, soc_update, soc_removesoc_snapshot, soc_diffsoc_integrate emits the generated top, .integrate.json, and review CSV. Preserve manual connection intent through a port-map JSON and refresh with soc_update; do not hand-edit generated instances.
Automatic shared-signal rules are suitable only for simple direction/width-compatible ports. Review multiple-driver, width, reset-domain, clock-domain, and protocol connections explicitly.
The built-in parser supports ANSI-style Verilog/SystemVerilog module ports. Unsupported syntax must fail explicitly rather than silently dropping ports. For interfaces, modports, complex package types, or non-ANSI declarations, provide a normalized wrapper before integration.