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Post-layout parasitic extraction + re-simulation for analog blocks — compares pre-layout vs post-layout specs. Use when the user says "post-layout resim", "extract and resimulate", "parasitic check", or at Step A7 of the analog track.
Codex または Claude でインストール この Prompt をコピーして Codex、Claude、または他のアシスタントに貼り付けると、Skill ページを確認してインストールできます。
SOC 職業分類に基づく
MANDATORY entry point when `design_one_shot_runner.step_rtl_gen` WAIVES with `fallback_skill='spec-to-rtl'`. This is invoked for every IC class with `rtl_gen=null` in `ic_class_registry.json` (currently: digital_arithmetic_primitive, digital_cmd_driven, bare_fpga, processor_cpu, unknown_protocol_class). The runner has already (1) ingested the prompt into L1-L27, (2) detected the IC class, (3) set the expected RTL path. This skill authors synthesizable RTL into the runner's expected path so the runner's downstream gates (chip_top auto-emit, rtl_hygiene_lint --fix, eda_lint, eda_synth, eco_loop, spec_conformance_check, full_stack_tb_gen) can fire on it. Triggered automatically by the runner's WAIVE message; also fires on phrases like 'AI invokes spec-to-rtl', 'runner WAIVED rtl_gen', 'spec-to-rtl handoff'. THIS IS THE RUNNER'S INTENDED PATH — NOT BYPASS. Bypass means authoring with MCP outside the runner's pipeline (what the 2026-05-28 wrong-shape RTLLM 37/50 did).
Closed-loop core-agent that fixes plugin issues filed by the field-agent. Invoke as a cron prompt; the loop polls the repo for ANY OPEN non-PR issue (new OR reopened — no label gating, no comment classifier), reproduces and fixes the bug chip-AGNOSTIC-ally, SELF-VERIFIES (reproduce + run the cadence-correct plugin test suite the CI way), then SHIPS by DIRECT PUSH (2026-06-26 owner directive — direct commit + `git push origin main`, no PR ceremony) gated by `gatekeeper_review.py --role core-agent` (MERGE_OK) + Step-2.7 + `gatekeeper_assign_version.py --write` (the pusher assigns the monotonic version pre-push) — posts a 繁體中文 fix comment in the canonical 5-section shape (incl 本機驗證 evidence), then `gh issue close` + adds the `core-closed` label. CLOSED is the terminal state; the field-agent audits closed issues on the real benchmark and reopens any it finds inadequate.
MANDATORY before landing any change to the FLOW itself — a gate, a check, a step, a phase runner, a verdict rule, or anything under programs/ that every design passes through. Flow-level changes are foundational: when they are right every cell benefits, and when they are wrong every cell lies at once and nobody notices. This skill is the acceptance standard for that class of change: bidirectional negative control (a test that cannot fail against the pre-fix code proves nothing), corpus sweep with zero false positives, prove-by-run that a gate declared BLOCKING actually stops the flow, no design/PDK/vendor literals, an explicit BLOCKING-vs-ADVISORY declaration, and degrade-loudly-never-silently. Every criterion here was written from a measured failure in this repo, cited inline. Triggers on: authoring or reviewing a gate/check/step, 'add a gate', 'this check should catch', 'why did the flow not catch', 'land a flow fix', 'flow-level change', '流程層改動', '加一個檢查', '這個 gate 為什麼沒擋住'.
When design_one_shot_runner.step_rtl_gen WAIVES rtl_gen and ip_catalog_query has emitted matches, this skill pulls the matched open-source IP RTL into the project's canonical phase2/stage1/rtl/ directory and authors only the integration wrapper / chip-top + OpenLane config glue from L1-L27 spec. Replaces full-from-scratch spec-to-rtl authoring for SoC-class designs where pre-validated open-source IPs exist in the catalog. Triggers automatically when phase2 WAIVES with `fallback_skill=catalog-glue-author`.
Read BEFORE authoring or revising an L-layer emitter, an L-layer schema field, or a layer gate. Answers the three questions no program can decide for you — WHICH of the 27 layers a given fact belongs in (the layer that CONSUMES it, not any layer that mentions it), WHETHER the thing you are specifying is structural (closed, enumerable, correct-by-construction, therefore a program) or behavioural (no unique correct implementation, therefore synthesis and not expansion), and WHETHER a declarative layer should align to IP-XACT / SystemRDL semantics instead of inventing schema. Produces a Layer Contract Decision record. Pairs with l_doc_consumer_contract.py.
Read Static Timing Analysis reports, triage setup/hold/recovery/removal violations, and propose fixes (RTL pipelining, sizing, useful skew, buffer insertion). Use when the user says "STA", "timing report", "timing violation", "setup fail", "hold fail", "close timing", "WNS", "TNS".
| name | analog-extraction-resim |
| description | Post-layout parasitic extraction + re-simulation for analog blocks — compares pre-layout vs post-layout specs. Use when the user says "post-layout resim", "extract and resimulate", "parasitic check", or at Step A7 of the analog track. |
After analog layout in Magic, extracts parasitic RC and re-simulates across PVT corners to check for layout-induced performance degradation. Compares pre-layout vs post-layout results and flags regressions.
analog-layout has produced a Magic .mag fileanalog/<block>/layout.mag — Magic layout fileanalog/<block>/corner_results.json — pre-layout SPICE results (baseline)analog/<block>/spec.json — specs for pass/fail comparisonExtract parasitics — emit/validate the Magic parasitic-RC TCL with
programs/magic_extract_spice_emit.py (do not hand-write the recipe):
# emit the deterministic .mag -> RC-annotated .subckt extraction TCL
python3 programs/magic_extract_spice_emit.py --block <block> \
--out-spice analog/<block>/<block>_extracted.spice --out extract.tcl
# or validate an existing extraction TCL (FAILs if it omits `extract all`
# or `ext2spice lvs` — the two silent causes of a vacuous 0% degradation)
python3 programs/magic_extract_spice_emit.py --validate extract.tcl
Then run it via eda_extraction (or magic). Output:
analog/<block>/<block>_extracted.spice.
The fixed
load / extract all / ext2spice lvs / ext2spicerecipe is enforced byprograms/magic_extract_spice_emit.py(distinct from the GDS-read + port-promote LVS recipe inmagic_port_extract_emit.py).
Re-simulate with extracted netlist:
eda_spice_corner with same corners as pre-layoutanalog/<block>/post_layout_corner_results.jsonCompare pre vs post — run the deterministic checker; do not re-grade by hand:
python3 programs/analog_pre_vs_post_layout_check.py <project> --json
It computes per-metric per-corner degradation (post - pre) / pre × 100% and
classifies it against the canonical degradation bands, which the program owns
(single source of truth — see "Degradation thresholds" below). Do NOT hardcode a
different ERROR/WARNING cutoff in your report; quote the program's verdict.
analog/<block>/pre_vs_post.json{
"block_name": "ldo_1v8",
"pre_layout_file": "corner_results.json",
"post_layout_file": "post_layout_corner_results.json",
"comparison": {
"gain_db": {"pre": 62.3, "post": 58.1, "degradation_pct": -6.7, "status": "OK"},
"ugb_mhz": {"pre": 11.2, "post": 7.5, "degradation_pct": -33.0, "status": "ERROR"},
"vout_dc": {"pre": 1.8002, "post": 1.7998, "degradation_pct": -0.02, "status": "OK"}
},
"worst_degradation": {"metric": "ugb_mhz", "pct": -33.0},
"overall_status": "NEEDS_RELAYOUT"
}
Enforced by programs/analog_pre_vs_post_layout_check.py (single source of
truth — ≤20% OK / >20% WARNING / >30% ERROR→NEEDS_RELAYOUT). Quote the
program's verdict; do not restate a conflicting cutoff. If the policy must
change, change it in the program (one place) so SKILL.md and runtime never drift.
Branch on the overall_status field emitted by
programs/analog_pre_vs_post_layout_check.py (deterministic, not a judgment call):
OK / WARNING → analog-hardmacro-gen (Step A8)NEEDS_RELAYOUT → back to analog-layout (Step A5)post_layout_corner_results.json → analog_pre_vs_post_layout_check gateAfter producing your output, save it to a file and run:
python3 plugins/vibe-ic/_shared/skill_compliance_check.py \
--requirements plugins/vibe-ic/skills/analog-extraction-resim/compliance.yaml \
<your_output_file>
Exit 0 = PASS, exit 1 = FAIL with specific missing elements listed.
Your task is not complete until the audit returns PASS.