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After analog_one_shot_runner emits A1..A9 outputs, AI spot-checks corner-sim coverage, hardmacro completeness, HIL data fidelity. Triggers on /vibe-ic-analog PASS or phrases like "review analog", "verify A8 hardmacro", "check analog corners".
Codex または Claude でインストール この Prompt をコピーして Codex、Claude、または他のアシスタントに貼り付けると、Skill ページを確認してインストールできます。
SOC 職業分類に基づく
MANDATORY entry point when `design_one_shot_runner.step_rtl_gen` WAIVES with `fallback_skill='spec-to-rtl'`. This is invoked for every IC class with `rtl_gen=null` in `ic_class_registry.json` (currently: digital_arithmetic_primitive, digital_cmd_driven, bare_fpga, processor_cpu, unknown_protocol_class). The runner has already (1) ingested the prompt into L1-L27, (2) detected the IC class, (3) set the expected RTL path. This skill authors synthesizable RTL into the runner's expected path so the runner's downstream gates (chip_top auto-emit, rtl_hygiene_lint --fix, eda_lint, eda_synth, eco_loop, spec_conformance_check, full_stack_tb_gen) can fire on it. Triggered automatically by the runner's WAIVE message; also fires on phrases like 'AI invokes spec-to-rtl', 'runner WAIVED rtl_gen', 'spec-to-rtl handoff'. THIS IS THE RUNNER'S INTENDED PATH — NOT BYPASS. Bypass means authoring with MCP outside the runner's pipeline (what the 2026-05-28 wrong-shape RTLLM 37/50 did).
Closed-loop core-agent that fixes plugin issues filed by the field-agent. Invoke as a cron prompt; the loop polls the repo for ANY OPEN non-PR issue (new OR reopened — no label gating, no comment classifier), reproduces and fixes the bug chip-AGNOSTIC-ally, SELF-VERIFIES (reproduce + run the cadence-correct plugin test suite the CI way), then SHIPS by DIRECT PUSH (2026-06-26 owner directive — direct commit + `git push origin main`, no PR ceremony) gated by `gatekeeper_review.py --role core-agent` (MERGE_OK) + Step-2.7 + `gatekeeper_assign_version.py --write` (the pusher assigns the monotonic version pre-push) — posts a 繁體中文 fix comment in the canonical 5-section shape (incl 本機驗證 evidence), then `gh issue close` + adds the `core-closed` label. CLOSED is the terminal state; the field-agent audits closed issues on the real benchmark and reopens any it finds inadequate.
MANDATORY before landing any change to the FLOW itself — a gate, a check, a step, a phase runner, a verdict rule, or anything under programs/ that every design passes through. Flow-level changes are foundational: when they are right every cell benefits, and when they are wrong every cell lies at once and nobody notices. This skill is the acceptance standard for that class of change: bidirectional negative control (a test that cannot fail against the pre-fix code proves nothing), corpus sweep with zero false positives, prove-by-run that a gate declared BLOCKING actually stops the flow, no design/PDK/vendor literals, an explicit BLOCKING-vs-ADVISORY declaration, and degrade-loudly-never-silently. Every criterion here was written from a measured failure in this repo, cited inline. Triggers on: authoring or reviewing a gate/check/step, 'add a gate', 'this check should catch', 'why did the flow not catch', 'land a flow fix', 'flow-level change', '流程層改動', '加一個檢查', '這個 gate 為什麼沒擋住'.
When design_one_shot_runner.step_rtl_gen WAIVES rtl_gen and ip_catalog_query has emitted matches, this skill pulls the matched open-source IP RTL into the project's canonical phase2/stage1/rtl/ directory and authors only the integration wrapper / chip-top + OpenLane config glue from L1-L27 spec. Replaces full-from-scratch spec-to-rtl authoring for SoC-class designs where pre-validated open-source IPs exist in the catalog. Triggers automatically when phase2 WAIVES with `fallback_skill=catalog-glue-author`.
Read BEFORE authoring or revising an L-layer emitter, an L-layer schema field, or a layer gate. Answers the three questions no program can decide for you — WHICH of the 27 layers a given fact belongs in (the layer that CONSUMES it, not any layer that mentions it), WHETHER the thing you are specifying is structural (closed, enumerable, correct-by-construction, therefore a program) or behavioural (no unique correct implementation, therefore synthesis and not expansion), and WHETHER a declarative layer should align to IP-XACT / SystemRDL semantics instead of inventing schema. Produces a Layer Contract Decision record. Pairs with l_doc_consumer_contract.py.
Read Static Timing Analysis reports, triage setup/hold/recovery/removal violations, and propose fixes (RTL pipelining, sizing, useful skew, buffer insertion). Use when the user says "STA", "timing report", "timing violation", "setup fail", "hold fail", "close timing", "WNS", "TNS".
| name | analog-output-verify |
| description | After analog_one_shot_runner emits A1..A9 outputs, AI spot-checks corner-sim coverage, hardmacro completeness, HIL data fidelity. Triggers on /vibe-ic-analog PASS or phrases like "review analog", "verify A8 hardmacro", "check analog corners". |
| tier | verification |
| paired_program | analog_one_shot_runner.py |
Purpose: analog runner is a thin chain marking each A1..A9 as PASS / WAIVED. WAIVED means human / domain skill needed. Even PASS steps need verification — analog correctness is rarely binary.
v1.6.14 Wave 90 — step renumber. Pre-release decimal/sub-step ids were integerised; the analog track is now A1-A9 (A1-A5 unchanged, per-block PV is A6, Resim/Hardmacro/Cosim are A7/A8/A9).
For each analog block in <project>/analog/<block>/:
Run the deterministic gates first, then apply the AI judgment below. Every fixed threshold / file-existence / structural rule on this track is enforced by a program — do not re-assert them by eye:
| Step | Gate | Enforces |
|---|---|---|
| A3 | programs/analog_a3_netlist_gen_check.py + programs/analog_netlist_pdk_check.py | .sp substance (.subckt, size), PDK model/body/device-name compliance |
| A4 | programs/analog_corner_margin_check.py | ≥27-corner PVT cube + ≥10% margin/corner (stricter than the 9-corner analog_corner_sweep_check.py); accepts A4_corners.json or corner_results.json, self-skips on stub |
| A5 | programs/analog_a5_layout_check.py | layout.mag/<block>.gds reference exists + DRC/LVS flags present |
| A6 | programs/analog_per_block_pv_completeness_check.py + programs/analog_a6_block_pv_check.py | full per-block deliverable set + DRC=0 / LVS=match evidence |
| A7 | programs/analog_pre_vs_post_layout_check.py (+ analog_a7_post_layout_resim_check.py) | post-vs-pre degradation bands (≤20% INFO / >20% WARN / >30% FAIL) |
| A8 | programs/analog_a8_hardmacro_gen_check.py + programs/analog_hardmacro_check.py | LEF+lib+GDS+Verilog present & non-stub |
| A8 outline | programs/analog_lef_gds_outline_check.py | LEF SIZE w BY h ; matches the GDS bounding box (the "LEF matches GDS outline" + "cross-check LEF outline vs A5 extents" spot-check, now a numeric gate; honest FAIL on mismatch / missing-half / garbage GDS) |
| A9 | programs/analog_hw_spice_correlation_check.py | HW-vs-SPICE error bands (<5% PASS / 5-15% WARN / >15% FAIL) |
python3 ../../programs/analog_corner_margin_check.py <project> \
--json <project>/reports/gates/analog_corner_margin.json
python3 ../../programs/analog_lef_gds_outline_check.py <project> \
--json <project>/reports/gates/analog_lef_gds_outline.json
# (the A1-A9 gates above run inside analog_one_shot_runner; re-run any
# individually if a verdict is in doubt)
Exit 0 = PASS (or self-skip / VACUOUS_PASS), 1 = FAIL. After every gate is green, apply the AI judgment below — these are the residual checks the programs cannot make.
analog_lef_gds_outline_check.py.analog-sizing-loop to retuneanalog-extraction-resim debuganalog-hw-tuning-loopAppend findings to <project>/reports/analog_verify.md.
After producing your output, save it to a file and run:
python3 ../../_shared/skill_compliance_check.py \
--requirements ./compliance.yaml <your_output_file>
Exit 0 = PASS, exit 1 = FAIL with the specific missing elements listed.
compliance.yaml (in this skill's directory) enumerates every required
element of your output — section headers, metadata fields, handoff lines,
tool invocations.
Your task is not complete until the audit returns PASS. If it fails, re-read the listed missing elements, patch your output, and re-run the audit.