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Audit RTL for reset-domain crossing hazards that are separate from clock-domain crossings. Use this skill whenever a design has multiple resets, asynchronous reset release behavior, or reset-bridged control paths that need structured review.
Codex 또는 Claude로 설치 이 Prompt를 복사해 Codex, Claude 또는 다른 어시스턴트에 붙여 넣으면 Skill 페이지를 검토하고 설치를 진행할 수 있습니다.
SOC 직업 분류 기준
Extract a source-grounded, AI-readable textual design view from HDL source, parser output, MCP tool output, or model reasoning. Use this skill when the user needs Verilog, SystemVerilog, VHDL, or proprietary hardware description language normalized into a reusable design view for downstream analysis flows such as timing, lint, CDC, RDC, formal planning, or DV planning. Prefer UHDM text for SystemVerilog/Verilog when available, AST JSON when UHDM is not available, and explicit model-derived views only when no tool evidence exists.
Analyze an HDL design view or visible RTL for pre-synthesis timing risk by estimating combinational logic depth on register-to-register and boundary timing paths. Use this skill when the user already has a UHDM text dump, AST JSON, source-grounded textual design view, or small visible RTL block and asks for critical paths, deep combinational logic, reg-to-reg timing risk, or pre-synthesis timing feedback. This skill is analysis-only; use an HDL-design-view extraction skill or flow when parser/tool/MCP selection, source-language normalization, or design-view generation is required.
Read an approved microarchitecture specification and emit synthesizable SystemVerilog with requirement traceability. Use this skill whenever the flow moves from block architecture into concrete RTL implementation.
Review synthesizable SystemVerilog for static RTL issues such as inferred latches, reset mismatches, width hazards, and multi-driver structure. Use this skill whenever generated RTL needs a deterministic front-end lint audit before CDC, RDC, or timing review.
Normalize a block-level design brief into deterministic requirements, explicit PPA targets, and open intake questions. Use this skill whenever the user provides high-level microarchitectural intent and the workflow must capture power, performance, and area before specification or RTL work begins.
Assemble normalized requirements, the microarchitecture spec, generated RTL, and static audit summaries into one front-end handoff package. Use this skill whenever the block-level RTL planning flow needs one deterministic output that can feed downstream DV planning.
| name | rtl-rdc-auditor |
| description | Audit RTL for reset-domain crossing hazards that are separate from clock-domain crossings. Use this skill whenever a design has multiple resets, asynchronous reset release behavior, or reset-bridged control paths that need structured review. |
Analyze block-level SystemVerilog for reset-domain crossing hazards and emit one structured RDC report.
Scope: block or small IP. This is a pre-EDA RDC audit, not a replacement for dedicated signoff tools.
Apply these repo rules before analysis and output generation:
../../rules/common/evidence-grounding.md../../rules/common/output-discipline.md../../rules/rdc/classification.mdRead the RTL and perform these steps:
../../rules/rdc/classification.md.Produce a single YAML document:
design:
top_module: event_counter
rtl_files:
- rtl/event_counter.sv
reset_domains:
- name: rst_n
active: active_low
style: async
line: 11
crossings:
- id: RDC-001
signal: irq_hold
source_reset: cfg_rst_n
dest_reset: rst_n
line: 42
protected: false
severity: high
description: "irq_hold is released by cfg_rst_n and sampled in logic released by rst_n without a visible reset bridge."
fix: "Stage the release into the destination reset domain or add an explicit reset bridge."
summary:
total_crossings: 1
violations: 1
by_severity:
critical: 0
high: 1
medium: 0
low: 0
info: 0