Generate a minimal blackbox/empty placeholder module (.empty.v) for a DUT by sampling its output port default values from a ksim FSDB waveform. Use when a DUT needs to be replaced by a stub (e.g., a CPU, accelerator, or DSP replaced by a non-functional placeholder) for SoC-level testing. The skill is DUT-agnostic: it works with any SystemVerilog/Verilog module whose FSDB waveform is available.
Analyze FSDB waveforms, debug simulation errors, explore netlist hierarchy, or run Verdi VIA apps in batch mode.
Generate uvm register-model companion headers (C .h for BSP and SystemVerilog .svh for testbench) from a Synopsys DesignWare IP databook text extract. Use when you need to produce project-convention RegDef.h/RegDef.svh files that match the layout used by `dv/simulation/verif_env/soc/header_files/` (one typedef-union per register, per-register offset + addr macros). The skill is IP-agnostic across Synopsys IP families (DW_apb_*, DW_axi_*, DWC_*) provided the input text uses the standard 'N.M.K REG_NAME' section markers and 'Table N-M Fields for Register: NAME' field tables.
Use when the user needs to analyze a design specification (PDF/document) and RTL source to extract verification-relevant information and produce a structured testplan. Covers： spec analysis, FSM extraction, register encoding analysis, and testplan generation. This is the first stage of a UVM verification pipeline -no EDA tools required.
Use when the user needs to generate UVM test cases and virtual sequences from a testplan. Produces test classes, virtual sequences, and updates testname.f. Each test follows the standard factory-registered pattern with raise/drop objection. Code generation only -compilation and simulation verification is Stage 5.