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Design and verify professional multi-sheet KiCad hierarchies generated from Circuit Weaver functional sections. Use when adding, splitting, renaming, or reviewing schematic sheets, cross-sheet interfaces, root symbols, sheet ownership, or final hierarchy ERC.
Codex 또는 Claude로 설치 이 Prompt를 복사해 Codex, Claude 또는 다른 어시스턴트에 붙여 넣으면 Skill 페이지를 검토하고 설치를 진행할 수 있습니다.
SOC 직업 분류 기준
Create, import, analyze, or resume an end-to-end Circuit Weaver electronic design with durable project state. Load the canonical workflow from skills/circuit-weaver/SKILL.md. Use kicad for one-off file inspection, bom for sourcing, and design-wizard only when explicitly requested.
Use only for an explicitly requested step-by-step Circuit Weaver questionnaire. Load the canonical workflow from skills/design-wizard/SKILL.md; use circuit-weaver for ordinary automatic new-design requests.
Route non-critical nets on a real KiCad PCB or Specctra DSN through Circuit Weaver's fail-closed Freerouting integration. Use after placement and net-class setup when the user requests autorouting, a validated SES session, routing diagnostics, or post-route cleanup. Keep critical power, RF, clock, crystal, switching, and differential nets manual.
Generate KiCad schematics from a Circuit Weaver design.yaml or a project's own checked-in generator. Use for large, repetitive, or machine-synchronized designs. Prefer the Circuit Weaver CLI unless the project actually contains and documents its own generation scripts.
Review Circuit Weaver's exhaustive placement proposal and apply approved SVG coordinates to a real electrically annotated KiCad PCB. Use after schematic generation for placement optimization, official-reference review, interactive SVG editing, strict reference reconciliation, and PCB placement handoff. Do not treat review artifacts as fabrication data.
Pin-to-net mapping auditor -- verifies that every IC pin in the schematic is connected to the correct net, matched against a pin map source of truth (CSV, datasheet table, or Python dict). Critical for BGA/QFN devices where swap errors are invisible to DRC/ERC.
| name | kicad-hierarchy |
| description | Design and verify professional multi-sheet KiCad hierarchies generated from Circuit Weaver functional sections. Use when adding, splitting, renaming, or reviewing schematic sheets, cross-sheet interfaces, root symbols, sheet ownership, or final hierarchy ERC. |
Treat the design spec as the source of truth. Do not hand-build or patch a root schematic with an assumed repository script.
Give every architectural block a stable unique id and explicit section:
blocks:
- id: input-protection
section: power_input
kind: template
type: protection
ref: D1
params:
protect_net: VIN
- id: system-regulator
section: power_regulation
kind: template
type: buck
ref: U2
params:
vin: 12
vout: 3.3
iout: 1.0
- id: main-controller
section: core_processing
kind: template
type: wireless_module
ref: U3
- id: external-connectors
section: external_io
kind: template
type: usb_c_connector
ref: J1
Use one section per major functional responsibility: input protection, each power stage, processing, sensors/analog front end, communications, external I/O, user interface, and debug/test. Do not collapse unrelated sections to save files. Generated decoupling, straps, pull-ups, and other support parts remain with their owning block.
circuit-weaver generate "${SPEC_PATH}" \
--output "${OUTPUT_DIR}" \
--require-kicad
Generation sanitizes and disambiguates sheet names, partitions oversized
sheets, creates the root hierarchy, and publishes all files atomically. Read
root_schematic and every child artifact from artifact_manifest.json;
never guess sheet filenames or assume main.kicad_sch.
--require-kicad is the final release-quality gate. Internal validation is
not a substitute for loading the exact final hierarchy in real KiCad and
running ERC.
artifact_manifest.json says kicad_verified: true and
verification_status: verified for a release-quality claim.After review, open the manifest-selected root in KiCad and run Update PCB from Schematic. Never route or manufacture from schematic review artifacts.