메뉴
The UART characterization-harness methodology - one host program running identically against cocotb sim and the FPGA. Sim transport, regmap-by-name, board bring-up gotchas (JTAG serials, ttyUSB). Use for any board characterization flow.
Codex 또는 Claude로 설치 이 Prompt를 복사해 Codex, Claude 또는 다른 어시스턴트에 붙여 넣으면 Skill 페이지를 검토하고 설치를 진행할 수 있습니다.
SOC 직업 분류 기준
Authoring a per-module reference page under docs/markdown (RTLCommon/RTLMath/RTLAmba) - the local .md style (header table, Overview, Architecture, Top-level Interface, Data model, Timing, Related, Test) and the SV header block that mirrors it. Use whenever you add or change an RTL block and need its docs/markdown page, and keep the book index in sync.
What kind of documentation lives where in this repo - handbook (method) vs docs/markdown (reader-facing) vs vault/Tasks (work) vs beside-code (CLAUDE.md, PRD). The rule that a beside-code README is a link, never a standalone guide, and that style guides / how-tos never live in the RTL tree. Use before creating, moving, or "tidying" any .md file, and when reviewing an area's meta-docs.
Coverage methodology - Verilator line/toggle coverage per component, functional coverage expectations, and the monbus packet-type coverage matrix. Use when adding tests, closing coverage, or preparing a board-gate sign-off.
The Sherpa documentation pipeline - md_to_docx with --style, LoF/LoT/LoW caption encoding, book indexes, RTL PDF generation, HAS/MAS vs operator guides. Use before generating or restructuring any deliverable doc.
Filelist rules - EVERY module MUST have a .f and MUST be registered in bin/filelists.toml. Components own their compile closure, consumers -f include, never hand-list another area's sources. Use when adding ANY new RTL module, test, or .f file.
Formal verification flow - SymbiYosys via sv2v flatten, in-RTL ifdef FORMAL properties, mutation-checking every new assertion, harness vacuity traps. Use when writing properties, regenerating proofs, or after changing any module with a formal dir.
| name | uart-harness |
| description | The UART characterization-harness methodology - one host program running identically against cocotb sim and the FPGA. Sim transport, regmap-by-name, board bring-up gotchas (JTAG serials, ttyUSB). Use for any board characterization flow. |
READ FIRST: vault/handbook/fpga/uart-harness.md (the handbook is the repo's memory; this skill is the signpost). One host program, sim + silicon; registers by name only. Board mechanics: vault/handbook/fpga/boards.md.
The handbook root is vault/handbook/INDEX.md - design/, dv/, fpga/ areas, atomic notes, wikilinked. When you learn a durable lesson in this domain, ADD IT TO THE HANDBOOK NOTE, not to this skill.
